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<div class="title">xnandps_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:gaf2f6aaad3157aafeda5749737e4d7d84"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gaf2f6aaad3157aafeda5749737e4d7d84">XNANDPS_MEMC_STATUS_OFFSET</a>&#160;&#160;&#160;0x000</td></tr>
<tr class="memdesc:gaf2f6aaad3157aafeda5749737e4d7d84"><td class="mdescLeft">&#160;</td><td class="mdescRight">Controller status reg, RO.  <a href="group__nandps.html#gaf2f6aaad3157aafeda5749737e4d7d84">More...</a><br/></td></tr>
<tr class="separator:gaf2f6aaad3157aafeda5749737e4d7d84"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4f1aeb2b315fdf74b1f6fcd4a5ba7273"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga4f1aeb2b315fdf74b1f6fcd4a5ba7273">XNANDPS_MEMC_IF_CONFIG_OFFSET</a>&#160;&#160;&#160;0x004</td></tr>
<tr class="memdesc:ga4f1aeb2b315fdf74b1f6fcd4a5ba7273"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interface config reg, RO.  <a href="group__nandps.html#ga4f1aeb2b315fdf74b1f6fcd4a5ba7273">More...</a><br/></td></tr>
<tr class="separator:ga4f1aeb2b315fdf74b1f6fcd4a5ba7273"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf90040ca8e85052266c805a409d4d128"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gaf90040ca8e85052266c805a409d4d128">XNANDPS_MEMC_SET_CONFIG_OFFSET</a>&#160;&#160;&#160;0x008</td></tr>
<tr class="memdesc:gaf90040ca8e85052266c805a409d4d128"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set configuration reg, WO.  <a href="group__nandps.html#gaf90040ca8e85052266c805a409d4d128">More...</a><br/></td></tr>
<tr class="separator:gaf90040ca8e85052266c805a409d4d128"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaaaf55b8085d1dcfcde3756a36c7ff41"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gaaaaf55b8085d1dcfcde3756a36c7ff41">XNANDPS_MEMC_CLR_CONFIG_OFFSET</a>&#160;&#160;&#160;0x00C</td></tr>
<tr class="memdesc:gaaaaf55b8085d1dcfcde3756a36c7ff41"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear config reg, WO.  <a href="group__nandps.html#gaaaaf55b8085d1dcfcde3756a36c7ff41">More...</a><br/></td></tr>
<tr class="separator:gaaaaf55b8085d1dcfcde3756a36c7ff41"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga80f534d4fe9ecc15457724440f014358"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga80f534d4fe9ecc15457724440f014358">XNANDPS_DIRECT_CMD_OFFSET</a>&#160;&#160;&#160;0x010</td></tr>
<tr class="memdesc:ga80f534d4fe9ecc15457724440f014358"><td class="mdescLeft">&#160;</td><td class="mdescRight">Direct command reg, WO.  <a href="group__nandps.html#ga80f534d4fe9ecc15457724440f014358">More...</a><br/></td></tr>
<tr class="separator:ga80f534d4fe9ecc15457724440f014358"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab5b751d38c7c8021092b14e6e85779d0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gab5b751d38c7c8021092b14e6e85779d0">XNANDPS_SET_CYCLES_OFFSET</a>&#160;&#160;&#160;0x014</td></tr>
<tr class="memdesc:gab5b751d38c7c8021092b14e6e85779d0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set cycles register, WO.  <a href="group__nandps.html#gab5b751d38c7c8021092b14e6e85779d0">More...</a><br/></td></tr>
<tr class="separator:gab5b751d38c7c8021092b14e6e85779d0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf26e745fd5b4f88aaa218e7cd8891041"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gaf26e745fd5b4f88aaa218e7cd8891041">XNANDPS_SET_OPMODE_OFFSET</a>&#160;&#160;&#160;0x018</td></tr>
<tr class="memdesc:gaf26e745fd5b4f88aaa218e7cd8891041"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set opmode register, WO.  <a href="group__nandps.html#gaf26e745fd5b4f88aaa218e7cd8891041">More...</a><br/></td></tr>
<tr class="separator:gaf26e745fd5b4f88aaa218e7cd8891041"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae47923a76310444937b2b3aa4a11e399"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gae47923a76310444937b2b3aa4a11e399">XNANDPS_REFRESH_PERIOD_0_OFFSET</a>&#160;&#160;&#160;0x020</td></tr>
<tr class="memdesc:gae47923a76310444937b2b3aa4a11e399"><td class="mdescLeft">&#160;</td><td class="mdescRight">Refresh period_0 reg, RW.  <a href="group__nandps.html#gae47923a76310444937b2b3aa4a11e399">More...</a><br/></td></tr>
<tr class="separator:gae47923a76310444937b2b3aa4a11e399"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga26d576acc9b981f1cfb8b40d94cf97c0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga26d576acc9b981f1cfb8b40d94cf97c0">XNANDPS_REFRESH_PERIOD_1_OFFSET</a>&#160;&#160;&#160;0x024</td></tr>
<tr class="memdesc:ga26d576acc9b981f1cfb8b40d94cf97c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Refresh period_1 reg, RW.  <a href="group__nandps.html#ga26d576acc9b981f1cfb8b40d94cf97c0">More...</a><br/></td></tr>
<tr class="separator:ga26d576acc9b981f1cfb8b40d94cf97c0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae800cae34e2924cc96d9a39dfec52c5e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gae800cae34e2924cc96d9a39dfec52c5e">XNANDPS_IF0_CHIP_0_CONFIG_OFFSET</a>&#160;&#160;&#160;0x100</td></tr>
<tr class="memdesc:gae800cae34e2924cc96d9a39dfec52c5e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interface 0 chip 0 config.  <a href="group__nandps.html#gae800cae34e2924cc96d9a39dfec52c5e">More...</a><br/></td></tr>
<tr class="separator:gae800cae34e2924cc96d9a39dfec52c5e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9b5790760ef234b80563ff98be33b639"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga9b5790760ef234b80563ff98be33b639">XNANDPS_IF0_CHIP_1_CONFIG_OFFSET</a>&#160;&#160;&#160;0x120</td></tr>
<tr class="memdesc:ga9b5790760ef234b80563ff98be33b639"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interface 0 chip 1 config.  <a href="group__nandps.html#ga9b5790760ef234b80563ff98be33b639">More...</a><br/></td></tr>
<tr class="separator:ga9b5790760ef234b80563ff98be33b639"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadca811b60bbf42b5e7c68df5f63b6b0b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gadca811b60bbf42b5e7c68df5f63b6b0b">XNANDPS_IF0_CHIP_2_CONFIG_OFFSET</a>&#160;&#160;&#160;0x140</td></tr>
<tr class="memdesc:gadca811b60bbf42b5e7c68df5f63b6b0b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interface 0 chip 2 config.  <a href="group__nandps.html#gadca811b60bbf42b5e7c68df5f63b6b0b">More...</a><br/></td></tr>
<tr class="separator:gadca811b60bbf42b5e7c68df5f63b6b0b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5a0d06b416b45bb4aee25db7136a00c2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga5a0d06b416b45bb4aee25db7136a00c2">XNANDPS_IF0_CHIP_3_CONFIG_OFFSET</a>&#160;&#160;&#160;0x160</td></tr>
<tr class="memdesc:ga5a0d06b416b45bb4aee25db7136a00c2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interface 0 chip 3 config.  <a href="group__nandps.html#ga5a0d06b416b45bb4aee25db7136a00c2">More...</a><br/></td></tr>
<tr class="separator:ga5a0d06b416b45bb4aee25db7136a00c2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae6eb4e6a228f126d327fbd05c0f014a8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gae6eb4e6a228f126d327fbd05c0f014a8">XNANDPS_IF1_CHIP_0_CONFIG_OFFSET</a>&#160;&#160;&#160;0x180</td></tr>
<tr class="memdesc:gae6eb4e6a228f126d327fbd05c0f014a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interface 1 chip 0 config.  <a href="group__nandps.html#gae6eb4e6a228f126d327fbd05c0f014a8">More...</a><br/></td></tr>
<tr class="separator:gae6eb4e6a228f126d327fbd05c0f014a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab2b15dbd88316137e9704ab6a80c648f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gab2b15dbd88316137e9704ab6a80c648f">XNANDPS_IF1_CHIP_1_CONFIG_OFFSET</a>&#160;&#160;&#160;0x1A0</td></tr>
<tr class="memdesc:gab2b15dbd88316137e9704ab6a80c648f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interface 1 chip 1 config.  <a href="group__nandps.html#gab2b15dbd88316137e9704ab6a80c648f">More...</a><br/></td></tr>
<tr class="separator:gab2b15dbd88316137e9704ab6a80c648f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0e9ddb24fb93c05cdf1bb345735d033c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga0e9ddb24fb93c05cdf1bb345735d033c">XNANDPS_IF1_CHIP_2_CONFIG_OFFSET</a>&#160;&#160;&#160;0x1C0</td></tr>
<tr class="memdesc:ga0e9ddb24fb93c05cdf1bb345735d033c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interface 1 chip 2 config.  <a href="group__nandps.html#ga0e9ddb24fb93c05cdf1bb345735d033c">More...</a><br/></td></tr>
<tr class="separator:ga0e9ddb24fb93c05cdf1bb345735d033c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabf861776417813a0b65b13e7d4dae0cf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gabf861776417813a0b65b13e7d4dae0cf">XNANDPS_IF1_CHIP_3_CONFIG_OFFSET</a>&#160;&#160;&#160;0x1E0</td></tr>
<tr class="memdesc:gabf861776417813a0b65b13e7d4dae0cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interface 1 chip 3 config.  <a href="group__nandps.html#gabf861776417813a0b65b13e7d4dae0cf">More...</a><br/></td></tr>
<tr class="separator:gabf861776417813a0b65b13e7d4dae0cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2913944cdf752a52c62581f2b6b92344"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga2913944cdf752a52c62581f2b6b92344">XNANDPS_FLASH_CYCLES</a>(addr)&#160;&#160;&#160;(0x000 + addr)</td></tr>
<tr class="memdesc:ga2913944cdf752a52c62581f2b6b92344"><td class="mdescLeft">&#160;</td><td class="mdescRight">NAND &amp; SRAM cycle,RO.  <a href="group__nandps.html#ga2913944cdf752a52c62581f2b6b92344">More...</a><br/></td></tr>
<tr class="separator:ga2913944cdf752a52c62581f2b6b92344"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9637bd6e50d1a65940625af864b6ee00"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga9637bd6e50d1a65940625af864b6ee00">XNANDPS_OPMODE</a>(addr)&#160;&#160;&#160;(0x004 + addr)</td></tr>
<tr class="memdesc:ga9637bd6e50d1a65940625af864b6ee00"><td class="mdescLeft">&#160;</td><td class="mdescRight">Chip opmode reg, RO.  <a href="group__nandps.html#ga9637bd6e50d1a65940625af864b6ee00">More...</a><br/></td></tr>
<tr class="separator:ga9637bd6e50d1a65940625af864b6ee00"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0e452979ec8c59e23b705f0e3da33eb6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga0e452979ec8c59e23b705f0e3da33eb6">XNANDPS_USER_STATUS_OFFSET</a>&#160;&#160;&#160;0x200</td></tr>
<tr class="memdesc:ga0e452979ec8c59e23b705f0e3da33eb6"><td class="mdescLeft">&#160;</td><td class="mdescRight">User status reg, RO.  <a href="group__nandps.html#ga0e452979ec8c59e23b705f0e3da33eb6">More...</a><br/></td></tr>
<tr class="separator:ga0e452979ec8c59e23b705f0e3da33eb6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf5e5c3cde493a3e91a3e98e5ff993a9e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gaf5e5c3cde493a3e91a3e98e5ff993a9e">XNANDPS_USER_CONFIG_OFFSET</a>&#160;&#160;&#160;0x204</td></tr>
<tr class="memdesc:gaf5e5c3cde493a3e91a3e98e5ff993a9e"><td class="mdescLeft">&#160;</td><td class="mdescRight">User config reg, WO.  <a href="group__nandps.html#gaf5e5c3cde493a3e91a3e98e5ff993a9e">More...</a><br/></td></tr>
<tr class="separator:gaf5e5c3cde493a3e91a3e98e5ff993a9e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga18178d8d0a8106de6362d8930a460b7b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga18178d8d0a8106de6362d8930a460b7b">XNANDPS_IF0_ECC_OFFSET</a>&#160;&#160;&#160;0x300</td></tr>
<tr class="memdesc:ga18178d8d0a8106de6362d8930a460b7b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interface 0 ECC register.  <a href="group__nandps.html#ga18178d8d0a8106de6362d8930a460b7b">More...</a><br/></td></tr>
<tr class="separator:ga18178d8d0a8106de6362d8930a460b7b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2c8cfb872b36a91ddd9780829e9065b6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga2c8cfb872b36a91ddd9780829e9065b6">XNANDPS_IF1_ECC_OFFSET</a>&#160;&#160;&#160;0x400</td></tr>
<tr class="memdesc:ga2c8cfb872b36a91ddd9780829e9065b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interface 1 ECC register.  <a href="group__nandps.html#ga2c8cfb872b36a91ddd9780829e9065b6">More...</a><br/></td></tr>
<tr class="separator:ga2c8cfb872b36a91ddd9780829e9065b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae4b738ea5a0e4c9cdbfd4952351747d1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gae4b738ea5a0e4c9cdbfd4952351747d1">XNANDPS_ECC_STATUS_OFFSET</a>(addr)&#160;&#160;&#160;(0x000 + addr)</td></tr>
<tr class="memdesc:gae4b738ea5a0e4c9cdbfd4952351747d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECC status register.  <a href="group__nandps.html#gae4b738ea5a0e4c9cdbfd4952351747d1">More...</a><br/></td></tr>
<tr class="separator:gae4b738ea5a0e4c9cdbfd4952351747d1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4e2e4acbbc22410dd5e6465065fb3c11"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga4e2e4acbbc22410dd5e6465065fb3c11">XNANDPS_ECC_MEMCFG_OFFSET</a>(addr)&#160;&#160;&#160;(0x004 + addr)</td></tr>
<tr class="memdesc:ga4e2e4acbbc22410dd5e6465065fb3c11"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECC mem config reg.  <a href="group__nandps.html#ga4e2e4acbbc22410dd5e6465065fb3c11">More...</a><br/></td></tr>
<tr class="separator:ga4e2e4acbbc22410dd5e6465065fb3c11"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga944a21dbf63f711c25e354be563fa302"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga944a21dbf63f711c25e354be563fa302">XNANDPS_ECC_MEMCMD1_OFFSET</a>(addr)&#160;&#160;&#160;(0x008 + addr)</td></tr>
<tr class="memdesc:ga944a21dbf63f711c25e354be563fa302"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECC mem com1 reg.  <a href="group__nandps.html#ga944a21dbf63f711c25e354be563fa302">More...</a><br/></td></tr>
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<tr class="memitem:ga2522d63c69de4aecc698d90c19e70521"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga2522d63c69de4aecc698d90c19e70521">XNANDPS_ECC_MEMCMD2_OFFSET</a>(addr)&#160;&#160;&#160;(0x00C + addr)</td></tr>
<tr class="memdesc:ga2522d63c69de4aecc698d90c19e70521"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECC mem com2 reg.  <a href="group__nandps.html#ga2522d63c69de4aecc698d90c19e70521">More...</a><br/></td></tr>
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<tr class="memitem:ga362aa8cde381fb04a9e93a47d13939a4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga362aa8cde381fb04a9e93a47d13939a4">XNANDPS_ECC_ADDR0_OFFSET</a>(addr)&#160;&#160;&#160;(0x010 + addr)</td></tr>
<tr class="memdesc:ga362aa8cde381fb04a9e93a47d13939a4"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECC address0 reg.  <a href="group__nandps.html#ga362aa8cde381fb04a9e93a47d13939a4">More...</a><br/></td></tr>
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<tr class="memitem:ga26401132963b086ae9a07280afd84636"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga26401132963b086ae9a07280afd84636">XNANDPS_ECC_ADDR1_OFFSET</a>(addr)&#160;&#160;&#160;(0x014 + addr)</td></tr>
<tr class="memdesc:ga26401132963b086ae9a07280afd84636"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECC address1 reg.  <a href="group__nandps.html#ga26401132963b086ae9a07280afd84636">More...</a><br/></td></tr>
<tr class="separator:ga26401132963b086ae9a07280afd84636"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7ed2fdfd7c0644b3b2f8ef41fb54afe3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga7ed2fdfd7c0644b3b2f8ef41fb54afe3">XNANDPS_ECC_VALUE0_OFFSET</a>(addr)&#160;&#160;&#160;(0x018 + addr)</td></tr>
<tr class="memdesc:ga7ed2fdfd7c0644b3b2f8ef41fb54afe3"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECC value 0 reg.  <a href="group__nandps.html#ga7ed2fdfd7c0644b3b2f8ef41fb54afe3">More...</a><br/></td></tr>
<tr class="separator:ga7ed2fdfd7c0644b3b2f8ef41fb54afe3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga32b23441f9771e755873f130b6b60585"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga32b23441f9771e755873f130b6b60585">XNANDPS_ECC_VALUE1_OFFSET</a>(addr)&#160;&#160;&#160;(0x01C + addr)</td></tr>
<tr class="memdesc:ga32b23441f9771e755873f130b6b60585"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECC value 1 reg.  <a href="group__nandps.html#ga32b23441f9771e755873f130b6b60585">More...</a><br/></td></tr>
<tr class="separator:ga32b23441f9771e755873f130b6b60585"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga824dbea2781ca306c1b7e5d4368151f4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga824dbea2781ca306c1b7e5d4368151f4">XNANDPS_ECC_VALUE2_OFFSET</a>(addr)&#160;&#160;&#160;(0x020 + addr)</td></tr>
<tr class="memdesc:ga824dbea2781ca306c1b7e5d4368151f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECC value 2 reg.  <a href="group__nandps.html#ga824dbea2781ca306c1b7e5d4368151f4">More...</a><br/></td></tr>
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<tr class="memitem:ga9452f9d35434dbf8da90939624bfd1ee"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga9452f9d35434dbf8da90939624bfd1ee">XNANDPS_ECC_VALUE3_OFFSET</a>(addr)&#160;&#160;&#160;(0x024 + addr)</td></tr>
<tr class="memdesc:ga9452f9d35434dbf8da90939624bfd1ee"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECC value 3 reg.  <a href="group__nandps.html#ga9452f9d35434dbf8da90939624bfd1ee">More...</a><br/></td></tr>
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<tr class="memitem:gafce755c5c24ab284c1a6ac1365933a87"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gafce755c5c24ab284c1a6ac1365933a87">XNANDPS_ECC_VALUE4_OFFSET</a>(addr)&#160;&#160;&#160;(0x028 + addr)</td></tr>
<tr class="memdesc:gafce755c5c24ab284c1a6ac1365933a87"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECC value 4 reg.  <a href="group__nandps.html#gafce755c5c24ab284c1a6ac1365933a87">More...</a><br/></td></tr>
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<tr class="memitem:ga4c5b3e833662553de1c24f553b367624"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga4c5b3e833662553de1c24f553b367624">XNANDPS_INTGTEST_OFFSET</a>&#160;&#160;&#160;0xE00</td></tr>
<tr class="memdesc:ga4c5b3e833662553de1c24f553b367624"><td class="mdescLeft">&#160;</td><td class="mdescRight">Integration test offset.  <a href="group__nandps.html#ga4c5b3e833662553de1c24f553b367624">More...</a><br/></td></tr>
<tr class="separator:ga4c5b3e833662553de1c24f553b367624"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga72bb3810df32f6b28f48c25ff98843c5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga72bb3810df32f6b28f48c25ff98843c5">XNANDPS_PERIPH_ID0_OFFSET</a>&#160;&#160;&#160;0xFE0</td></tr>
<tr class="memdesc:ga72bb3810df32f6b28f48c25ff98843c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Peripheral id0 register.  <a href="group__nandps.html#ga72bb3810df32f6b28f48c25ff98843c5">More...</a><br/></td></tr>
<tr class="separator:ga72bb3810df32f6b28f48c25ff98843c5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac770d392ac287ea3385cd79aeb6f976e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gac770d392ac287ea3385cd79aeb6f976e">XNANDPS_PERIPH_ID1_OFFSET</a>&#160;&#160;&#160;0xFE4</td></tr>
<tr class="memdesc:gac770d392ac287ea3385cd79aeb6f976e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Peripheral id1 register.  <a href="group__nandps.html#gac770d392ac287ea3385cd79aeb6f976e">More...</a><br/></td></tr>
<tr class="separator:gac770d392ac287ea3385cd79aeb6f976e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8b0719eb74f224d3a0b9644ab413d6c0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga8b0719eb74f224d3a0b9644ab413d6c0">XNANDPS_PERIPH_ID2_OFFSET</a>&#160;&#160;&#160;0xFE8</td></tr>
<tr class="memdesc:ga8b0719eb74f224d3a0b9644ab413d6c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Peripheral id2 register.  <a href="group__nandps.html#ga8b0719eb74f224d3a0b9644ab413d6c0">More...</a><br/></td></tr>
<tr class="separator:ga8b0719eb74f224d3a0b9644ab413d6c0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7cd6dde2cd6f64e7c316d5401c8a63f4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga7cd6dde2cd6f64e7c316d5401c8a63f4">XNANDPS_PERIPH_ID3_OFFSET</a>&#160;&#160;&#160;0xFEC</td></tr>
<tr class="memdesc:ga7cd6dde2cd6f64e7c316d5401c8a63f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Peripheral id3 register.  <a href="group__nandps.html#ga7cd6dde2cd6f64e7c316d5401c8a63f4">More...</a><br/></td></tr>
<tr class="separator:ga7cd6dde2cd6f64e7c316d5401c8a63f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga993171014887eebcf39861f9502645fb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga993171014887eebcf39861f9502645fb">XNANDPS_PCELL_ID0_OFFSET</a>&#160;&#160;&#160;0xFF0</td></tr>
<tr class="memdesc:ga993171014887eebcf39861f9502645fb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Primecell id0 register.  <a href="group__nandps.html#ga993171014887eebcf39861f9502645fb">More...</a><br/></td></tr>
<tr class="separator:ga993171014887eebcf39861f9502645fb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3fdee65c36e6f735ec675870e643e12a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga3fdee65c36e6f735ec675870e643e12a">XNANDPS_PCELL_ID1_OFFSET</a>&#160;&#160;&#160;0xFF4</td></tr>
<tr class="memdesc:ga3fdee65c36e6f735ec675870e643e12a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Primecell id1 register.  <a href="group__nandps.html#ga3fdee65c36e6f735ec675870e643e12a">More...</a><br/></td></tr>
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<tr class="memitem:gae5d1c3ff379ebe21f078020df844d957"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gae5d1c3ff379ebe21f078020df844d957">XNANDPS_PCELL_ID2_OFFSET</a>&#160;&#160;&#160;0xFF8</td></tr>
<tr class="memdesc:gae5d1c3ff379ebe21f078020df844d957"><td class="mdescLeft">&#160;</td><td class="mdescRight">Primecell id2 register.  <a href="group__nandps.html#gae5d1c3ff379ebe21f078020df844d957">More...</a><br/></td></tr>
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<tr class="memitem:gafe10153d3fb48e1a0445e0b5c822eca7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gafe10153d3fb48e1a0445e0b5c822eca7">XNANDPS_PCELL_ID3_OFFSET</a>&#160;&#160;&#160;0xFFC</td></tr>
<tr class="memdesc:gafe10153d3fb48e1a0445e0b5c822eca7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Primecell id3 register.  <a href="group__nandps.html#gafe10153d3fb48e1a0445e0b5c822eca7">More...</a><br/></td></tr>
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<tr class="memitem:ab1c9ec799c4b10aba366c1333b36d98b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#ab1c9ec799c4b10aba366c1333b36d98b">XNandPs_ReadReg</a>&#160;&#160;&#160;Xil_In32</td></tr>
<tr class="memdesc:ab1c9ec799c4b10aba366c1333b36d98b"><td class="mdescLeft">&#160;</td><td class="mdescRight">XNandPs Register register.  <a href="#ab1c9ec799c4b10aba366c1333b36d98b">More...</a><br/></td></tr>
<tr class="separator:ab1c9ec799c4b10aba366c1333b36d98b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac87bcc9e0fec61b2b02b9a434962e576"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#ac87bcc9e0fec61b2b02b9a434962e576">XNandPs_WriteReg</a>&#160;&#160;&#160;Xil_Out32</td></tr>
<tr class="memdesc:ac87bcc9e0fec61b2b02b9a434962e576"><td class="mdescLeft">&#160;</td><td class="mdescRight">XNandPs register write.  <a href="#ac87bcc9e0fec61b2b02b9a434962e576">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Memory controller status register bit definitions and masks</div></td></tr>
<tr class="memitem:ga29483de4ec80b0072f9a83152551bd60"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga29483de4ec80b0072f9a83152551bd60">XNANDPS_MEMC_STATUS_STATE_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga29483de4ec80b0072f9a83152551bd60"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller operating state mask.  <a href="group__nandps.html#ga29483de4ec80b0072f9a83152551bd60">More...</a><br/></td></tr>
<tr class="separator:ga29483de4ec80b0072f9a83152551bd60"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6f0072315e38b85a92b15334524ede70"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga6f0072315e38b85a92b15334524ede70">XNANDPS_MEMC_STATUS_INT_EN0_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga6f0072315e38b85a92b15334524ede70"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface 0 interrupt enable mask.  <a href="group__nandps.html#ga6f0072315e38b85a92b15334524ede70">More...</a><br/></td></tr>
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<tr class="memitem:gaf30fae0b6374003158bb30ab205e5066"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gaf30fae0b6374003158bb30ab205e5066">XNANDPS_MEMC_STATUS_INT_EN1_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gaf30fae0b6374003158bb30ab205e5066"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface 1 interrupt enable mask.  <a href="group__nandps.html#gaf30fae0b6374003158bb30ab205e5066">More...</a><br/></td></tr>
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<tr class="memitem:ga1af4d9860270663419e0ddc9e3b1f8a0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga1af4d9860270663419e0ddc9e3b1f8a0">XNANDPS_MEMC_STATUS_INT_STATUS0_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga1af4d9860270663419e0ddc9e3b1f8a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface 0 interrupt status mask.  <a href="group__nandps.html#ga1af4d9860270663419e0ddc9e3b1f8a0">More...</a><br/></td></tr>
<tr class="separator:ga1af4d9860270663419e0ddc9e3b1f8a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga96e53f19a9d2a7a0c4a6fff79892861b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga96e53f19a9d2a7a0c4a6fff79892861b">XNANDPS_MEMC_STATUS_INT_STATUS1_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga96e53f19a9d2a7a0c4a6fff79892861b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface 1 interrupt status mask.  <a href="group__nandps.html#ga96e53f19a9d2a7a0c4a6fff79892861b">More...</a><br/></td></tr>
<tr class="separator:ga96e53f19a9d2a7a0c4a6fff79892861b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad362d9c01b74e4718aec176a6bcb7be8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gad362d9c01b74e4718aec176a6bcb7be8">XNANDPS_MEMC_STATUS_RAW_INT_STATUS0_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:gad362d9c01b74e4718aec176a6bcb7be8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface 0 raw interrupt status mask.  <a href="group__nandps.html#gad362d9c01b74e4718aec176a6bcb7be8">More...</a><br/></td></tr>
<tr class="separator:gad362d9c01b74e4718aec176a6bcb7be8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga995c16a409a39580d52421c7fea17d78"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga995c16a409a39580d52421c7fea17d78">XNANDPS_MEMC_STATUS_RAW_INT_STATUS1_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga995c16a409a39580d52421c7fea17d78"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface 1 raw interrupt status mask.  <a href="group__nandps.html#ga995c16a409a39580d52421c7fea17d78">More...</a><br/></td></tr>
<tr class="separator:ga995c16a409a39580d52421c7fea17d78"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga09acbe1735a88477b192a20f23677ee4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga09acbe1735a88477b192a20f23677ee4">XNANDPS_MEMC_STATUS_ECC_INT_EN0_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:ga09acbe1735a88477b192a20f23677ee4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface 0 ECC interrupt enable mask.  <a href="group__nandps.html#ga09acbe1735a88477b192a20f23677ee4">More...</a><br/></td></tr>
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<tr class="memitem:ga2cb62df85f4a206172d3fd51c52bdc8b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga2cb62df85f4a206172d3fd51c52bdc8b">XNANDPS_MEMC_STATUS_ECC_INT_EN1_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:ga2cb62df85f4a206172d3fd51c52bdc8b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface 1 ECC interrupt enable mask.  <a href="group__nandps.html#ga2cb62df85f4a206172d3fd51c52bdc8b">More...</a><br/></td></tr>
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<tr class="memitem:ga07b9ad8c6a16aa1309dade3eea7d75b7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga07b9ad8c6a16aa1309dade3eea7d75b7">XNANDPS_MEMC_STATUS_ECC_INT0_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:ga07b9ad8c6a16aa1309dade3eea7d75b7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface 0 ECC interrupt status mask.  <a href="group__nandps.html#ga07b9ad8c6a16aa1309dade3eea7d75b7">More...</a><br/></td></tr>
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<tr class="memitem:ga30acc1fb063eeca5441e48e8c1a57e66"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga30acc1fb063eeca5441e48e8c1a57e66">XNANDPS_MEMC_STATUS_ECC_INT1_MASK</a>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="memdesc:ga30acc1fb063eeca5441e48e8c1a57e66"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface 1 ECC interrupt status mask.  <a href="group__nandps.html#ga30acc1fb063eeca5441e48e8c1a57e66">More...</a><br/></td></tr>
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<tr class="memitem:ga49bab818d758f198cb953244842cd2a5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga49bab818d758f198cb953244842cd2a5">XNANDPS_MEMC_STATUS_RAW_ECC_INT0_MASK</a>&#160;&#160;&#160;0x00000800</td></tr>
<tr class="memdesc:ga49bab818d758f198cb953244842cd2a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface 0 raw ECC interrupt status mask.  <a href="group__nandps.html#ga49bab818d758f198cb953244842cd2a5">More...</a><br/></td></tr>
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<tr class="memitem:ga6b66a736fe774f3b6d91390ed1e5da66"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga6b66a736fe774f3b6d91390ed1e5da66">XNANDPS_MEMC_STATUS_RAW_ECC_INT1_MASK</a>&#160;&#160;&#160;0x00001000</td></tr>
<tr class="memdesc:ga6b66a736fe774f3b6d91390ed1e5da66"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface 1 raw ECC interrupt status mask.  <a href="group__nandps.html#ga6b66a736fe774f3b6d91390ed1e5da66">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Memory interface configurartion register bit definitions and masks</div></td></tr>
<tr class="memitem:gae2e056f5a0dc7c034d7fcad40321a711"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gae2e056f5a0dc7c034d7fcad40321a711">XNANDPS_MEMC_IF_CONFIG_MEMORY_TYPE0_MASK</a>&#160;&#160;&#160;0x00000003</td></tr>
<tr class="memdesc:gae2e056f5a0dc7c034d7fcad40321a711"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface 0 type mask.  <a href="group__nandps.html#gae2e056f5a0dc7c034d7fcad40321a711">More...</a><br/></td></tr>
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<tr class="memitem:gacfa52ce957918afd7a5e2b9002e8e5ca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gacfa52ce957918afd7a5e2b9002e8e5ca">XNANDPS_MEMC_IF_CONFIG_MEMORY_CHIPS0_MASK</a>&#160;&#160;&#160;0x0000000C</td></tr>
<tr class="memdesc:gacfa52ce957918afd7a5e2b9002e8e5ca"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface 0 chip select mask.  <a href="group__nandps.html#gacfa52ce957918afd7a5e2b9002e8e5ca">More...</a><br/></td></tr>
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<tr class="memitem:ga43dea45efbf4a537f2802c9a82e2a45a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga43dea45efbf4a537f2802c9a82e2a45a">XNANDPS_MEMC_IF_CONFIG_MEMORY_WIDTH0_MASK</a>&#160;&#160;&#160;0x00000030</td></tr>
<tr class="memdesc:ga43dea45efbf4a537f2802c9a82e2a45a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface 0 data width mask.  <a href="group__nandps.html#ga43dea45efbf4a537f2802c9a82e2a45a">More...</a><br/></td></tr>
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<tr class="memitem:ga33221cbade48b01c3c517fa4b93fc036"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga33221cbade48b01c3c517fa4b93fc036">XNANDPS_MEMC_IF_CONFIG_REMAP0_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga33221cbade48b01c3c517fa4b93fc036"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface 0 remap0 mask.  <a href="group__nandps.html#ga33221cbade48b01c3c517fa4b93fc036">More...</a><br/></td></tr>
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<tr class="memitem:ga6a41616bcbac0f34890a4f46bb83b674"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga6a41616bcbac0f34890a4f46bb83b674">XNANDPS_MEMC_IF_CONFIG_MEMORY_TYPE1_MASK</a>&#160;&#160;&#160;0x00000300</td></tr>
<tr class="memdesc:ga6a41616bcbac0f34890a4f46bb83b674"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface 1 type mask.  <a href="group__nandps.html#ga6a41616bcbac0f34890a4f46bb83b674">More...</a><br/></td></tr>
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<tr class="memitem:ga349af4d8dc505a62352e7410be68625d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga349af4d8dc505a62352e7410be68625d">XNANDPS_MEMC_IF_CONFIG_MEMORY_CHIPS1_MASK</a>&#160;&#160;&#160;0x00000C00</td></tr>
<tr class="memdesc:ga349af4d8dc505a62352e7410be68625d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface 1 chip select mask.  <a href="group__nandps.html#ga349af4d8dc505a62352e7410be68625d">More...</a><br/></td></tr>
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<tr class="memitem:ga241956eb1862c1125c1109b8cbea6249"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga241956eb1862c1125c1109b8cbea6249">XNANDPS_MEMC_IF_CONFIG_MEMORY_WIDTH1_MASK</a>&#160;&#160;&#160;0x00003000</td></tr>
<tr class="memdesc:ga241956eb1862c1125c1109b8cbea6249"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface 1 data width mask.  <a href="group__nandps.html#ga241956eb1862c1125c1109b8cbea6249">More...</a><br/></td></tr>
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<tr class="memitem:gae712856a973b4fbe2f6caeaa1460c00f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gae712856a973b4fbe2f6caeaa1460c00f">XNANDPS_MEMC_IF_CONFIG_REMAP1_MASK</a>&#160;&#160;&#160;0x00004000</td></tr>
<tr class="memdesc:gae712856a973b4fbe2f6caeaa1460c00f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface 1 remap0 mask.  <a href="group__nandps.html#gae712856a973b4fbe2f6caeaa1460c00f">More...</a><br/></td></tr>
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<tr class="memitem:ga1472881c10164bcb840a040a6a3b81ef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga1472881c10164bcb840a040a6a3b81ef">XNANDPS_MEMC_IF_CONFIG_EX_MONITORS_MASK</a>&#160;&#160;&#160;0x00030000</td></tr>
<tr class="memdesc:ga1472881c10164bcb840a040a6a3b81ef"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface exclusive masks mask.  <a href="group__nandps.html#ga1472881c10164bcb840a040a6a3b81ef">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Set configuration register bit definitions and masks</div></td></tr>
<tr class="memitem:ga6082962ed33a2f188a55b670ca7c5871"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga6082962ed33a2f188a55b670ca7c5871">XNANDPS_MEMC_SET_CONFIG_INT_ENABLE0_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga6082962ed33a2f188a55b670ca7c5871"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interfce0 interrupt enable mask.  <a href="group__nandps.html#ga6082962ed33a2f188a55b670ca7c5871">More...</a><br/></td></tr>
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<tr class="memitem:ga2cef5fd83b8590859349ff957638c152"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga2cef5fd83b8590859349ff957638c152">XNANDPS_MEMC_SET_CONFIG_INT_ENABLE1_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga2cef5fd83b8590859349ff957638c152"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interfce1 interrupt enable mask.  <a href="group__nandps.html#ga2cef5fd83b8590859349ff957638c152">More...</a><br/></td></tr>
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<tr class="memitem:ga561848b2dd77bfd2f541a74a45cd186d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga561848b2dd77bfd2f541a74a45cd186d">XNANDPS_MEMC_SET_CONFIG_LOW_POWER_REQ_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga561848b2dd77bfd2f541a74a45cd186d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller low power state mask.  <a href="group__nandps.html#ga561848b2dd77bfd2f541a74a45cd186d">More...</a><br/></td></tr>
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<tr class="memitem:ga39ac41c2239851ad104bf96f7e03ba8b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga39ac41c2239851ad104bf96f7e03ba8b">XNANDPS_MEMC_SET_CONFIG_ECC_INT_ENABLE0_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga39ac41c2239851ad104bf96f7e03ba8b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interfce0 ECC interrupt enable mask.  <a href="group__nandps.html#ga39ac41c2239851ad104bf96f7e03ba8b">More...</a><br/></td></tr>
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<tr class="memitem:ga89f0d8effcd9d8822d0a460fbbbbd85e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga89f0d8effcd9d8822d0a460fbbbbd85e">XNANDPS_MEMC_SET_CONFIG_ECC_INT_ENABLE1_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga89f0d8effcd9d8822d0a460fbbbbd85e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interfce1 ECC interrupt enable mask.  <a href="group__nandps.html#ga89f0d8effcd9d8822d0a460fbbbbd85e">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Clear configuration register bit definitions and masks</div></td></tr>
<tr class="memitem:ga6c962a9097a503fed1c61d2e8339fbaf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga6c962a9097a503fed1c61d2e8339fbaf">XNANDPS_MEMC_CLR_CONFIG_INT_DISABLE0_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga6c962a9097a503fed1c61d2e8339fbaf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface 0 interrupt disable mask.  <a href="group__nandps.html#ga6c962a9097a503fed1c61d2e8339fbaf">More...</a><br/></td></tr>
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<tr class="memitem:ga6731d845acda751402ee26f71588253e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga6731d845acda751402ee26f71588253e">XNANDPS_MEMC_CLR_CONFIG_INT_DISABLE1_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga6731d845acda751402ee26f71588253e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface 1 interrupt disable mask.  <a href="group__nandps.html#ga6731d845acda751402ee26f71588253e">More...</a><br/></td></tr>
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<tr class="memitem:gaefe9ae62cf92675d965af9e54f5c4c14"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gaefe9ae62cf92675d965af9e54f5c4c14">XNANDPS_MEMC_CLR_CONFIG_LOW_POWER_EXIT_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gaefe9ae62cf92675d965af9e54f5c4c14"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller low power exit mask.  <a href="group__nandps.html#gaefe9ae62cf92675d965af9e54f5c4c14">More...</a><br/></td></tr>
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<tr class="memitem:ga00ca72eb11e3697d1d19920f94fbafcf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga00ca72eb11e3697d1d19920f94fbafcf">XNANDPS_MEMC_CLR_CONFIG_INT_CLR0_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga00ca72eb11e3697d1d19920f94fbafcf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface0 interrupt clear mask.  <a href="group__nandps.html#ga00ca72eb11e3697d1d19920f94fbafcf">More...</a><br/></td></tr>
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<tr class="memitem:ga0c56dde06594c0e2a7deac16d7291f4a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga0c56dde06594c0e2a7deac16d7291f4a">XNANDPS_MEMC_CLR_CONFIG_INT_CLR1_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga0c56dde06594c0e2a7deac16d7291f4a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface1 interrupt clear mask.  <a href="group__nandps.html#ga0c56dde06594c0e2a7deac16d7291f4a">More...</a><br/></td></tr>
<tr class="separator:ga0c56dde06594c0e2a7deac16d7291f4a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa80abd762794a6e6eee8e7e7b763e563"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gaa80abd762794a6e6eee8e7e7b763e563">XNANDPS_MEMC_CLR_CONFIG_ECC_INT_DISABLE0_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:gaa80abd762794a6e6eee8e7e7b763e563"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface0 ECC interrupt disable mask.  <a href="group__nandps.html#gaa80abd762794a6e6eee8e7e7b763e563">More...</a><br/></td></tr>
<tr class="separator:gaa80abd762794a6e6eee8e7e7b763e563"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa1b2d0e0a22463d92e6308573fa72e7b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gaa1b2d0e0a22463d92e6308573fa72e7b">XNANDPS_MEMC_CLR_CONFIG_ECC_INT_DISABLE1_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:gaa1b2d0e0a22463d92e6308573fa72e7b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory controller interface1 ECC interrupt disable mask.  <a href="group__nandps.html#gaa1b2d0e0a22463d92e6308573fa72e7b">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Clear configuration register bit definitions and masks and shift</div></td></tr>
<tr class="memitem:ga72263dd095a25af894b0c05fd9f4937f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga72263dd095a25af894b0c05fd9f4937f">XNANDPS_DIRECT_CMD_ADDR_MASK</a>&#160;&#160;&#160;0x000FFFFF</td></tr>
<tr class="memdesc:ga72263dd095a25af894b0c05fd9f4937f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Direct command address mask.  <a href="group__nandps.html#ga72263dd095a25af894b0c05fd9f4937f">More...</a><br/></td></tr>
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<tr class="memitem:ga4e38ce9f7d66e8bcc75bc9164b4be851"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga4e38ce9f7d66e8bcc75bc9164b4be851">XNANDPS_DIRECT_CMD_SET_CRE_MASK</a>&#160;&#160;&#160;0x00100000</td></tr>
<tr class="memdesc:ga4e38ce9f7d66e8bcc75bc9164b4be851"><td class="mdescLeft">&#160;</td><td class="mdescRight">Direct command set cre mask.  <a href="group__nandps.html#ga4e38ce9f7d66e8bcc75bc9164b4be851">More...</a><br/></td></tr>
<tr class="separator:ga4e38ce9f7d66e8bcc75bc9164b4be851"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae58e7e151541e1043a63f0005efa50e8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gae58e7e151541e1043a63f0005efa50e8">XNANDPS_DIRECT_CMD_TYPE_MASK</a>&#160;&#160;&#160;0x00600000</td></tr>
<tr class="memdesc:gae58e7e151541e1043a63f0005efa50e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Direct command type mask.  <a href="group__nandps.html#gae58e7e151541e1043a63f0005efa50e8">More...</a><br/></td></tr>
<tr class="separator:gae58e7e151541e1043a63f0005efa50e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga506db1c7923585401372d904ff590cff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga506db1c7923585401372d904ff590cff">XNANDPS_DIRECT_CMD_CHIP_SELECT_MASK</a>&#160;&#160;&#160;0x03800000</td></tr>
<tr class="memdesc:ga506db1c7923585401372d904ff590cff"><td class="mdescLeft">&#160;</td><td class="mdescRight">Direct command chip select mask.  <a href="group__nandps.html#ga506db1c7923585401372d904ff590cff">More...</a><br/></td></tr>
<tr class="separator:ga506db1c7923585401372d904ff590cff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga23a01036fc8434fa034b45b05f07853e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga23a01036fc8434fa034b45b05f07853e">XNANDPS_DIRECT_CMD_SET_CRE_SHIFT</a>&#160;&#160;&#160;20</td></tr>
<tr class="memdesc:ga23a01036fc8434fa034b45b05f07853e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Direct command set_cre shift.  <a href="group__nandps.html#ga23a01036fc8434fa034b45b05f07853e">More...</a><br/></td></tr>
<tr class="separator:ga23a01036fc8434fa034b45b05f07853e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafa1f198d318f573ae07d63bd50f6b869"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gafa1f198d318f573ae07d63bd50f6b869">XNANDPS_DIRECT_CMD_CMD_TYPE_SHIFT</a>&#160;&#160;&#160;21</td></tr>
<tr class="memdesc:gafa1f198d318f573ae07d63bd50f6b869"><td class="mdescLeft">&#160;</td><td class="mdescRight">Direct command cmd_type shift.  <a href="group__nandps.html#gafa1f198d318f573ae07d63bd50f6b869">More...</a><br/></td></tr>
<tr class="separator:gafa1f198d318f573ae07d63bd50f6b869"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga60b7e5a5ea3d06e82d69e73a0e0f8494"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga60b7e5a5ea3d06e82d69e73a0e0f8494">XNANDPS_DIRECT_CMD_CHIP_SELECT_SHIFT</a>&#160;&#160;&#160;23</td></tr>
<tr class="memdesc:ga60b7e5a5ea3d06e82d69e73a0e0f8494"><td class="mdescLeft">&#160;</td><td class="mdescRight">Direct command chip select shift.  <a href="group__nandps.html#ga60b7e5a5ea3d06e82d69e73a0e0f8494">More...</a><br/></td></tr>
<tr class="separator:ga60b7e5a5ea3d06e82d69e73a0e0f8494"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Set cycles register bit definitions and masks and shift</div></td></tr>
<tr class="memitem:gae5a16bc2a803077eadc2eb82bda51014"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gae5a16bc2a803077eadc2eb82bda51014">XNANDPS_SET_CYCLES_SET_T0_MASK</a>&#160;&#160;&#160;0x0000000F</td></tr>
<tr class="memdesc:gae5a16bc2a803077eadc2eb82bda51014"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set cycles set_t0 mask.  <a href="group__nandps.html#gae5a16bc2a803077eadc2eb82bda51014">More...</a><br/></td></tr>
<tr class="separator:gae5a16bc2a803077eadc2eb82bda51014"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7e253d9418908a0dff9d4eb90f8fa353"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga7e253d9418908a0dff9d4eb90f8fa353">XNANDPS_SET_CYCLES_SET_T1_MASK</a>&#160;&#160;&#160;0x000000F0</td></tr>
<tr class="memdesc:ga7e253d9418908a0dff9d4eb90f8fa353"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set cycles set_t1 mask.  <a href="group__nandps.html#ga7e253d9418908a0dff9d4eb90f8fa353">More...</a><br/></td></tr>
<tr class="separator:ga7e253d9418908a0dff9d4eb90f8fa353"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae31a2657dd2d6aaa70668956cb35e12e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gae31a2657dd2d6aaa70668956cb35e12e">XNANDPS_SET_CYCLES_SET_T2_MASK</a>&#160;&#160;&#160;0x00000700</td></tr>
<tr class="memdesc:gae31a2657dd2d6aaa70668956cb35e12e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set cycles set_t2 mask.  <a href="group__nandps.html#gae31a2657dd2d6aaa70668956cb35e12e">More...</a><br/></td></tr>
<tr class="separator:gae31a2657dd2d6aaa70668956cb35e12e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaad0f4bc1000e4f9d221fa36c5525fe0e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gaad0f4bc1000e4f9d221fa36c5525fe0e">XNANDPS_SET_CYCLES_SET_T3_MASK</a>&#160;&#160;&#160;0x00003800</td></tr>
<tr class="memdesc:gaad0f4bc1000e4f9d221fa36c5525fe0e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set cycles set_t3 mask.  <a href="group__nandps.html#gaad0f4bc1000e4f9d221fa36c5525fe0e">More...</a><br/></td></tr>
<tr class="separator:gaad0f4bc1000e4f9d221fa36c5525fe0e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7ad602e799d2de40bd6a62100afb3c4a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga7ad602e799d2de40bd6a62100afb3c4a">XNANDPS_SET_CYCLES_SET_T4_MASK</a>&#160;&#160;&#160;0x0001C000</td></tr>
<tr class="memdesc:ga7ad602e799d2de40bd6a62100afb3c4a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set cycles set_t4 mask.  <a href="group__nandps.html#ga7ad602e799d2de40bd6a62100afb3c4a">More...</a><br/></td></tr>
<tr class="separator:ga7ad602e799d2de40bd6a62100afb3c4a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa569f1daeb322a081c11b9b4d5a5a708"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gaa569f1daeb322a081c11b9b4d5a5a708">XNANDPS_SET_CYCLES_SET_T5_MASK</a>&#160;&#160;&#160;0x000E0000</td></tr>
<tr class="memdesc:gaa569f1daeb322a081c11b9b4d5a5a708"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set cycles set_t5 mask.  <a href="group__nandps.html#gaa569f1daeb322a081c11b9b4d5a5a708">More...</a><br/></td></tr>
<tr class="separator:gaa569f1daeb322a081c11b9b4d5a5a708"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a2e2fafd72b42c85dcdb2c8162e0965"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga0a2e2fafd72b42c85dcdb2c8162e0965">XNANDPS_SET_CYCLES_SET_T6_MASK</a>&#160;&#160;&#160;0x00F00000</td></tr>
<tr class="memdesc:ga0a2e2fafd72b42c85dcdb2c8162e0965"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set cycles set_t6 mask.  <a href="group__nandps.html#ga0a2e2fafd72b42c85dcdb2c8162e0965">More...</a><br/></td></tr>
<tr class="separator:ga0a2e2fafd72b42c85dcdb2c8162e0965"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadee7fbf6528bf5313dffa4bf649fd21a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gadee7fbf6528bf5313dffa4bf649fd21a">XNANDPS_SET_CYCLES_SET_T0_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:gadee7fbf6528bf5313dffa4bf649fd21a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set cycles set_t0 shift.  <a href="group__nandps.html#gadee7fbf6528bf5313dffa4bf649fd21a">More...</a><br/></td></tr>
<tr class="separator:gadee7fbf6528bf5313dffa4bf649fd21a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga08c26709c536d595bfac4df5c37ce033"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga08c26709c536d595bfac4df5c37ce033">XNANDPS_SET_CYCLES_SET_T1_SHIFT</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:ga08c26709c536d595bfac4df5c37ce033"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set cycles set_t1 shift.  <a href="group__nandps.html#ga08c26709c536d595bfac4df5c37ce033">More...</a><br/></td></tr>
<tr class="separator:ga08c26709c536d595bfac4df5c37ce033"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga220b55cb89b463abfcf4b68e5647b138"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga220b55cb89b463abfcf4b68e5647b138">XNANDPS_SET_CYCLES_SET_T2_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:ga220b55cb89b463abfcf4b68e5647b138"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set cycles set_t2 shift.  <a href="group__nandps.html#ga220b55cb89b463abfcf4b68e5647b138">More...</a><br/></td></tr>
<tr class="separator:ga220b55cb89b463abfcf4b68e5647b138"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9d07c93a998ce446b1e3f13feb398779"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga9d07c93a998ce446b1e3f13feb398779">XNANDPS_SET_CYCLES_SET_T3_SHIFT</a>&#160;&#160;&#160;11</td></tr>
<tr class="memdesc:ga9d07c93a998ce446b1e3f13feb398779"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set cycles set_t3 shift.  <a href="group__nandps.html#ga9d07c93a998ce446b1e3f13feb398779">More...</a><br/></td></tr>
<tr class="separator:ga9d07c93a998ce446b1e3f13feb398779"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad04f832bbbc70b63a72e35f1b4f04506"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gad04f832bbbc70b63a72e35f1b4f04506">XNANDPS_SET_CYCLES_SET_T4_SHIFT</a>&#160;&#160;&#160;14</td></tr>
<tr class="memdesc:gad04f832bbbc70b63a72e35f1b4f04506"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set cycles set_t4 shift.  <a href="group__nandps.html#gad04f832bbbc70b63a72e35f1b4f04506">More...</a><br/></td></tr>
<tr class="separator:gad04f832bbbc70b63a72e35f1b4f04506"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac6131810c9cd8eab374f752b8865ba62"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gac6131810c9cd8eab374f752b8865ba62">XNANDPS_SET_CYCLES_SET_T5_SHIFT</a>&#160;&#160;&#160;17</td></tr>
<tr class="memdesc:gac6131810c9cd8eab374f752b8865ba62"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set cycles set_t5 shift.  <a href="group__nandps.html#gac6131810c9cd8eab374f752b8865ba62">More...</a><br/></td></tr>
<tr class="separator:gac6131810c9cd8eab374f752b8865ba62"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad3f4d14c66ae3392d3a230cd09573b69"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gad3f4d14c66ae3392d3a230cd09573b69">XNANDPS_SET_CYCLES_SET_T6_SHIFT</a>&#160;&#160;&#160;20</td></tr>
<tr class="memdesc:gad3f4d14c66ae3392d3a230cd09573b69"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set cycles set_t6 shift.  <a href="group__nandps.html#gad3f4d14c66ae3392d3a230cd09573b69">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Set opmode register bit definitions and masks</div></td></tr>
<tr class="memitem:ga98fd193d788dedc6b2d825b8b948b2ed"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga98fd193d788dedc6b2d825b8b948b2ed">XNANDPS_SET_OPMODE_SET_MW_MASK</a>&#160;&#160;&#160;0x00000003</td></tr>
<tr class="memdesc:ga98fd193d788dedc6b2d825b8b948b2ed"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set opmode set memory width mask.  <a href="group__nandps.html#ga98fd193d788dedc6b2d825b8b948b2ed">More...</a><br/></td></tr>
<tr class="separator:ga98fd193d788dedc6b2d825b8b948b2ed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga90a5a64d521f386167f189bcc0d7f326"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga90a5a64d521f386167f189bcc0d7f326">XNANDPS_SET_OPMODE_SET_RD_SYNC_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga90a5a64d521f386167f189bcc0d7f326"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set opmode set rd_sync mask.  <a href="group__nandps.html#ga90a5a64d521f386167f189bcc0d7f326">More...</a><br/></td></tr>
<tr class="separator:ga90a5a64d521f386167f189bcc0d7f326"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga74133e97289fbaae73f5840bdbc86c6c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga74133e97289fbaae73f5840bdbc86c6c">XNANDPS_SET_OPMODE_SET_RD_BL_MASK</a>&#160;&#160;&#160;0x00000038</td></tr>
<tr class="memdesc:ga74133e97289fbaae73f5840bdbc86c6c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set opmode set rd_bl mask.  <a href="group__nandps.html#ga74133e97289fbaae73f5840bdbc86c6c">More...</a><br/></td></tr>
<tr class="separator:ga74133e97289fbaae73f5840bdbc86c6c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf3c17ec72aae7428a4688cec0d0bf1d0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gaf3c17ec72aae7428a4688cec0d0bf1d0">XNANDPS_SET_OPMODE_SET_WR_SYNC_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:gaf3c17ec72aae7428a4688cec0d0bf1d0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set opmode set wr_sync mask.  <a href="group__nandps.html#gaf3c17ec72aae7428a4688cec0d0bf1d0">More...</a><br/></td></tr>
<tr class="separator:gaf3c17ec72aae7428a4688cec0d0bf1d0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae2a7e1c5828216658ec8f24d28619316"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gae2a7e1c5828216658ec8f24d28619316">XNANDPS_SET_OPMODE_SET_WR_BL_MASK</a>&#160;&#160;&#160;0x00000380</td></tr>
<tr class="memdesc:gae2a7e1c5828216658ec8f24d28619316"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set opmode set wr_bl mask.  <a href="group__nandps.html#gae2a7e1c5828216658ec8f24d28619316">More...</a><br/></td></tr>
<tr class="separator:gae2a7e1c5828216658ec8f24d28619316"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaf1078a0cd3a518d97f86bb57fc8476c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gaaf1078a0cd3a518d97f86bb57fc8476c">XNANDPS_SET_OPMODE_SET_BAA_MASK</a>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="memdesc:gaaf1078a0cd3a518d97f86bb57fc8476c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set opmode set baa mask.  <a href="group__nandps.html#gaaf1078a0cd3a518d97f86bb57fc8476c">More...</a><br/></td></tr>
<tr class="separator:gaaf1078a0cd3a518d97f86bb57fc8476c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf7b4e287660ee6239f00dc15a9ba66ce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gaf7b4e287660ee6239f00dc15a9ba66ce">XNANDPS_SET_OPMODE_SET_ADV_MASK</a>&#160;&#160;&#160;0x00000800</td></tr>
<tr class="memdesc:gaf7b4e287660ee6239f00dc15a9ba66ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set opmode set adv mask.  <a href="group__nandps.html#gaf7b4e287660ee6239f00dc15a9ba66ce">More...</a><br/></td></tr>
<tr class="separator:gaf7b4e287660ee6239f00dc15a9ba66ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad43885a434da3b3ee177638e3728cd54"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gad43885a434da3b3ee177638e3728cd54">XNANDPS_SET_OPMODE_SET_BLS_MASK</a>&#160;&#160;&#160;0x00001000</td></tr>
<tr class="memdesc:gad43885a434da3b3ee177638e3728cd54"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set opmode set bls mask.  <a href="group__nandps.html#gad43885a434da3b3ee177638e3728cd54">More...</a><br/></td></tr>
<tr class="separator:gad43885a434da3b3ee177638e3728cd54"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0dba075cba1636a90d20c3c804217d6a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga0dba075cba1636a90d20c3c804217d6a">XNANDPS_SET_OPMODE_SET_BURST_ALIGN_MASK</a>&#160;&#160;&#160;0x0000E000</td></tr>
<tr class="memdesc:ga0dba075cba1636a90d20c3c804217d6a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set opmode set burst align mask.  <a href="group__nandps.html#ga0dba075cba1636a90d20c3c804217d6a">More...</a><br/></td></tr>
<tr class="separator:ga0dba075cba1636a90d20c3c804217d6a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae56ca80625221b651da0d080d2cf7a55"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gae56ca80625221b651da0d080d2cf7a55">XNANDPS_SET_OPMODE_MW_8_BITS</a>&#160;&#160;&#160;0x0</td></tr>
<tr class="memdesc:gae56ca80625221b651da0d080d2cf7a55"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set opmode memory width value for 8-bit flash.  <a href="group__nandps.html#gae56ca80625221b651da0d080d2cf7a55">More...</a><br/></td></tr>
<tr class="separator:gae56ca80625221b651da0d080d2cf7a55"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacafee1faf2214361e9a96833f1078060"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gacafee1faf2214361e9a96833f1078060">XNANDPS_SET_OPMODE_MW_16_BITS</a>&#160;&#160;&#160;0x1</td></tr>
<tr class="memdesc:gacafee1faf2214361e9a96833f1078060"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set opmode memory width value for 16-bit flash.  <a href="group__nandps.html#gacafee1faf2214361e9a96833f1078060">More...</a><br/></td></tr>
<tr class="separator:gacafee1faf2214361e9a96833f1078060"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7bc4a75576c5dd9e5c1d20cde377c3b7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga7bc4a75576c5dd9e5c1d20cde377c3b7">XNANDPS_SET_OPMODE_MW_32_BITS</a>&#160;&#160;&#160;0x2</td></tr>
<tr class="memdesc:ga7bc4a75576c5dd9e5c1d20cde377c3b7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set opmode memory width value for 32-bit flash.  <a href="group__nandps.html#ga7bc4a75576c5dd9e5c1d20cde377c3b7">More...</a><br/></td></tr>
<tr class="separator:ga7bc4a75576c5dd9e5c1d20cde377c3b7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Refresh period register bit definitions and masks</div></td></tr>
<tr class="memitem:ga7a36cf1959895976367117cd48bbd72e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga7a36cf1959895976367117cd48bbd72e">XNANDPS_REFRESH_PERIOD_0_MASK</a>&#160;&#160;&#160;0x0000000F</td></tr>
<tr class="memdesc:ga7a36cf1959895976367117cd48bbd72e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interface 0 refresh period mask.  <a href="group__nandps.html#ga7a36cf1959895976367117cd48bbd72e">More...</a><br/></td></tr>
<tr class="separator:ga7a36cf1959895976367117cd48bbd72e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0831d64aea2f14c4db5f10d0feabc3fd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga0831d64aea2f14c4db5f10d0feabc3fd">XNANDPS_REFRESH_PERIOD_1_MASK</a>&#160;&#160;&#160;0x0000000F</td></tr>
<tr class="memdesc:ga0831d64aea2f14c4db5f10d0feabc3fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interface 1 refresh period mask.  <a href="group__nandps.html#ga0831d64aea2f14c4db5f10d0feabc3fd">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Opmode register bit definitions and masks</div></td></tr>
<tr class="memitem:gabdc2b81c4e5d74c4006ddf575c9d722d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gabdc2b81c4e5d74c4006ddf575c9d722d">XNANDPS_OPMODE_MW_MASK</a>&#160;&#160;&#160;0x00000003</td></tr>
<tr class="memdesc:gabdc2b81c4e5d74c4006ddf575c9d722d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Opmode Memory width mask.  <a href="group__nandps.html#gabdc2b81c4e5d74c4006ddf575c9d722d">More...</a><br/></td></tr>
<tr class="separator:gabdc2b81c4e5d74c4006ddf575c9d722d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad376300216ec8a7e5f702077bee6751b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gad376300216ec8a7e5f702077bee6751b">XNANDPS_OPMODE_RD_SYNC_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gad376300216ec8a7e5f702077bee6751b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Opmode rd_sync mask.  <a href="group__nandps.html#gad376300216ec8a7e5f702077bee6751b">More...</a><br/></td></tr>
<tr class="separator:gad376300216ec8a7e5f702077bee6751b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga58d19a511781c10256342d2595e51eaf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga58d19a511781c10256342d2595e51eaf">XNANDPS_OPMODE_RD_BL_MASK</a>&#160;&#160;&#160;0x00000038</td></tr>
<tr class="memdesc:ga58d19a511781c10256342d2595e51eaf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Opmode rd_bl mask.  <a href="group__nandps.html#ga58d19a511781c10256342d2595e51eaf">More...</a><br/></td></tr>
<tr class="separator:ga58d19a511781c10256342d2595e51eaf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad21ff934be607af5a71e218f1faca5aa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gad21ff934be607af5a71e218f1faca5aa">XNANDPS_OPMODE_WR_SYNC_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:gad21ff934be607af5a71e218f1faca5aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Opmode wr_sync mask.  <a href="group__nandps.html#gad21ff934be607af5a71e218f1faca5aa">More...</a><br/></td></tr>
<tr class="separator:gad21ff934be607af5a71e218f1faca5aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae5074a539f489b9228ff72a63e12b43b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gae5074a539f489b9228ff72a63e12b43b">XNANDPS_OPMODE_WR_BL_MASK</a>&#160;&#160;&#160;0x00000380</td></tr>
<tr class="memdesc:gae5074a539f489b9228ff72a63e12b43b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Opmode BAA mask.  <a href="group__nandps.html#gae5074a539f489b9228ff72a63e12b43b">More...</a><br/></td></tr>
<tr class="separator:gae5074a539f489b9228ff72a63e12b43b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacba2b496fcdc7f962b2921cd4cd2deb7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gacba2b496fcdc7f962b2921cd4cd2deb7">XNANDPS_OPMODE_BAA_MASK</a>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="memdesc:gacba2b496fcdc7f962b2921cd4cd2deb7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Opmode ADV mask.  <a href="group__nandps.html#gacba2b496fcdc7f962b2921cd4cd2deb7">More...</a><br/></td></tr>
<tr class="separator:gacba2b496fcdc7f962b2921cd4cd2deb7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacb0ea4d313e8298a55444b93f6ed32e2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gacb0ea4d313e8298a55444b93f6ed32e2">XNANDPS_OPMODE_ADV_MASK</a>&#160;&#160;&#160;0x00000800</td></tr>
<tr class="memdesc:gacb0ea4d313e8298a55444b93f6ed32e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Opmode BLS mask.  <a href="group__nandps.html#gacb0ea4d313e8298a55444b93f6ed32e2">More...</a><br/></td></tr>
<tr class="separator:gacb0ea4d313e8298a55444b93f6ed32e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga963d73c5157a53b1e06d24246ccbb79b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga963d73c5157a53b1e06d24246ccbb79b">XNANDPS_OPMODE_BLS_MASK</a>&#160;&#160;&#160;0x00001000</td></tr>
<tr class="memdesc:ga963d73c5157a53b1e06d24246ccbb79b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Opmode Burst align mask.  <a href="group__nandps.html#ga963d73c5157a53b1e06d24246ccbb79b">More...</a><br/></td></tr>
<tr class="separator:ga963d73c5157a53b1e06d24246ccbb79b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5d6d64e992e78a19e5e7b355231b551f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga5d6d64e992e78a19e5e7b355231b551f">XNANDPS_OPMODE_BURST_ALIGN_MASK</a>&#160;&#160;&#160;0x0000E000</td></tr>
<tr class="memdesc:ga5d6d64e992e78a19e5e7b355231b551f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Opmode Address mask.  <a href="group__nandps.html#ga5d6d64e992e78a19e5e7b355231b551f">More...</a><br/></td></tr>
<tr class="separator:ga5d6d64e992e78a19e5e7b355231b551f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabb85102f0e483da786c914991e5113b1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gabb85102f0e483da786c914991e5113b1">XNANDPS_OPMODE_ADDRESS_MASK</a>&#160;&#160;&#160;0x00FF0000</td></tr>
<tr class="memdesc:gabb85102f0e483da786c914991e5113b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Opmode Address match mask.  <a href="group__nandps.html#gabb85102f0e483da786c914991e5113b1">More...</a><br/></td></tr>
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<tr class="memitem:ga4ada4edbda611dda5d4ce9e3a5dfc76b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4ada4edbda611dda5d4ce9e3a5dfc76b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XNANDPS_OPMODE_ADDRESS_MATCH_MASK</b>&#160;&#160;&#160;0xFF000000</td></tr>
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<tr><td colspan="2"><div class="groupHeader">User status register bit definitions and masks</div></td></tr>
<tr class="memitem:ga58e0615789d4e654d3143fcee3b30075"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga58e0615789d4e654d3143fcee3b30075">XNANDPS_USER_STATUS_MASK</a>&#160;&#160;&#160;0x000000FF</td></tr>
<tr class="memdesc:ga58e0615789d4e654d3143fcee3b30075"><td class="mdescLeft">&#160;</td><td class="mdescRight">User status mask.  <a href="group__nandps.html#ga58e0615789d4e654d3143fcee3b30075">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">User config register bit definitions and masks</div></td></tr>
<tr class="memitem:ga64695bd0d2752a225bcf02660dbba330"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga64695bd0d2752a225bcf02660dbba330">XNANDPS_USER_CONFIG_MASK</a>&#160;&#160;&#160;0x000000FF</td></tr>
<tr class="memdesc:ga64695bd0d2752a225bcf02660dbba330"><td class="mdescLeft">&#160;</td><td class="mdescRight">User config mask.  <a href="group__nandps.html#ga64695bd0d2752a225bcf02660dbba330">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">ECC status register bit definitions and masks</div></td></tr>
<tr class="memitem:gad6eb5b7dc7a24721002d68a6e958229a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gad6eb5b7dc7a24721002d68a6e958229a">XNANDPS_ECC_STATUS_RAW_INT_STATUS_MASK</a>&#160;&#160;&#160;0x0000003F</td></tr>
<tr class="memdesc:gad6eb5b7dc7a24721002d68a6e958229a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc status raw_int_status mask.  <a href="group__nandps.html#gad6eb5b7dc7a24721002d68a6e958229a">More...</a><br/></td></tr>
<tr class="separator:gad6eb5b7dc7a24721002d68a6e958229a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga076dbfca456968a745059a51673e7ec3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga076dbfca456968a745059a51673e7ec3">XNANDPS_ECC_STATUS_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga076dbfca456968a745059a51673e7ec3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc status ecc_status mask.  <a href="group__nandps.html#ga076dbfca456968a745059a51673e7ec3">More...</a><br/></td></tr>
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<tr class="memitem:ga99835434f14906b82e037592893a06c3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga99835434f14906b82e037592893a06c3">XNANDPS_ECC_LAST_MASK</a>&#160;&#160;&#160;0x00000180</td></tr>
<tr class="memdesc:ga99835434f14906b82e037592893a06c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc status ecc_last mask.  <a href="group__nandps.html#ga99835434f14906b82e037592893a06c3">More...</a><br/></td></tr>
<tr class="separator:ga99835434f14906b82e037592893a06c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga277de987357ffa3e1fe572f07e7ca474"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga277de987357ffa3e1fe572f07e7ca474">XNANDPS_ECC_READ_NOT_WRITE_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:ga277de987357ffa3e1fe572f07e7ca474"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc status ecc_read_not_write mask.  <a href="group__nandps.html#ga277de987357ffa3e1fe572f07e7ca474">More...</a><br/></td></tr>
<tr class="separator:ga277de987357ffa3e1fe572f07e7ca474"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad9c67a22528be2256f47d1883324a9d8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gad9c67a22528be2256f47d1883324a9d8">XNANDPS_ECC_VALID_MASK</a>&#160;&#160;&#160;0x00007C00</td></tr>
<tr class="memdesc:gad9c67a22528be2256f47d1883324a9d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc status ecc_valid mask.  <a href="group__nandps.html#gad9c67a22528be2256f47d1883324a9d8">More...</a><br/></td></tr>
<tr class="separator:gad9c67a22528be2256f47d1883324a9d8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa0126861c9885e18631a341b9c502654"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gaa0126861c9885e18631a341b9c502654">XNANDPS_ECC_FAIL_MASK</a>&#160;&#160;&#160;0x000F8000</td></tr>
<tr class="memdesc:gaa0126861c9885e18631a341b9c502654"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc status ecc_fail mask.  <a href="group__nandps.html#gaa0126861c9885e18631a341b9c502654">More...</a><br/></td></tr>
<tr class="separator:gaa0126861c9885e18631a341b9c502654"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga50e521a56f9e03bc5ec2a26be318cedb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga50e521a56f9e03bc5ec2a26be318cedb">XNANDPS_ECC_CAN_CORRECT_MASK</a>&#160;&#160;&#160;0x01F00000</td></tr>
<tr class="memdesc:ga50e521a56f9e03bc5ec2a26be318cedb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc status ecc_can_correct mask.  <a href="group__nandps.html#ga50e521a56f9e03bc5ec2a26be318cedb">More...</a><br/></td></tr>
<tr class="separator:ga50e521a56f9e03bc5ec2a26be318cedb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8ff69e4d141ed6d7a3d7847af23ba7df"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga8ff69e4d141ed6d7a3d7847af23ba7df">XNANDPS_ECC_READ_MASK</a>&#160;&#160;&#160;0x37000000</td></tr>
<tr class="memdesc:ga8ff69e4d141ed6d7a3d7847af23ba7df"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc status ecc_read mask.  <a href="group__nandps.html#ga8ff69e4d141ed6d7a3d7847af23ba7df">More...</a><br/></td></tr>
<tr class="separator:ga8ff69e4d141ed6d7a3d7847af23ba7df"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">ECC mem config register bit definitions and masks and shifts</div></td></tr>
<tr class="memitem:ga30bb8644de65c2fcc2293102531b16be"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga30bb8644de65c2fcc2293102531b16be">XNANDPS_ECC_MEMCFG_PAGE_SIZE_MASK</a>&#160;&#160;&#160;0x00000003</td></tr>
<tr class="memdesc:ga30bb8644de65c2fcc2293102531b16be"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc cfg page_size mask.  <a href="group__nandps.html#ga30bb8644de65c2fcc2293102531b16be">More...</a><br/></td></tr>
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<tr class="memitem:gabedfedca80335cfdbcc1987e9b122aeb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gabedfedca80335cfdbcc1987e9b122aeb">XNANDPS_ECC_MEMCFG_ECC_MODE_MASK</a>&#160;&#160;&#160;0x0000000C</td></tr>
<tr class="memdesc:gabedfedca80335cfdbcc1987e9b122aeb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc cfg ecc_mode mask.  <a href="group__nandps.html#gabedfedca80335cfdbcc1987e9b122aeb">More...</a><br/></td></tr>
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<tr class="memitem:ga0767b20d534c69ad8befd2dd66b0ddc5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga0767b20d534c69ad8befd2dd66b0ddc5">XNANDPS_ECC_MEMCFG_ECC_READ_END_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga0767b20d534c69ad8befd2dd66b0ddc5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc cfg ecc_read_end mask.  <a href="group__nandps.html#ga0767b20d534c69ad8befd2dd66b0ddc5">More...</a><br/></td></tr>
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<tr class="memitem:ga27bf1e2feb352151c2a1f66fbb649480"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga27bf1e2feb352151c2a1f66fbb649480">XNANDPS_ECC_MEMCFG_ECC_JUMP_MASK</a>&#160;&#160;&#160;0x00000060</td></tr>
<tr class="memdesc:ga27bf1e2feb352151c2a1f66fbb649480"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc cfg ecc_jump mask.  <a href="group__nandps.html#ga27bf1e2feb352151c2a1f66fbb649480">More...</a><br/></td></tr>
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<tr class="memitem:ga142d4677fab71f33eaf73279805484d7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga142d4677fab71f33eaf73279805484d7">XNANDPS_ECC_MEMCFG_IGNORE_ADD8_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:ga142d4677fab71f33eaf73279805484d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc cfg ecc_ignore_add_eight mask.  <a href="group__nandps.html#ga142d4677fab71f33eaf73279805484d7">More...</a><br/></td></tr>
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<tr class="memitem:ga94c64bf32eec92e13cee977f774ad531"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga94c64bf32eec92e13cee977f774ad531">XNANDPS_ECC_MEMCFG_ECC_INT_PASS_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:ga94c64bf32eec92e13cee977f774ad531"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc cfg ecc_int_pass mask.  <a href="group__nandps.html#ga94c64bf32eec92e13cee977f774ad531">More...</a><br/></td></tr>
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<tr class="memitem:gaa5bb5adec17b9bf55b505698e4b1e711"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gaa5bb5adec17b9bf55b505698e4b1e711">XNANDPS_ECC_MEMCFG_ECC_INT_ABORT_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:gaa5bb5adec17b9bf55b505698e4b1e711"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc cfg ecc_int_abort mask.  <a href="group__nandps.html#gaa5bb5adec17b9bf55b505698e4b1e711">More...</a><br/></td></tr>
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<tr class="memitem:gaa59b3fee4580c8944c3c14301f2a0c5f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gaa59b3fee4580c8944c3c14301f2a0c5f">XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_MASK</a>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="memdesc:gaa59b3fee4580c8944c3c14301f2a0c5f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc cfg ecc_extra_block mask.  <a href="group__nandps.html#gaa59b3fee4580c8944c3c14301f2a0c5f">More...</a><br/></td></tr>
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<tr class="memitem:ga440ae7de6be7e30c19f4defb0d5a02fc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga440ae7de6be7e30c19f4defb0d5a02fc">XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SIZE_MASK</a>&#160;&#160;&#160;0x00001800</td></tr>
<tr class="memdesc:ga440ae7de6be7e30c19f4defb0d5a02fc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc cfg ecc_extra_block_size mask.  <a href="group__nandps.html#ga440ae7de6be7e30c19f4defb0d5a02fc">More...</a><br/></td></tr>
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<tr class="memitem:ga8e2bf64e4dc971ef51817d5ab3c7a3a8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga8e2bf64e4dc971ef51817d5ab3c7a3a8">XNANDPS_ECC_MEMCFG_PAGE_SIZE_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga8e2bf64e4dc971ef51817d5ab3c7a3a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc cfg page_size shift.  <a href="group__nandps.html#ga8e2bf64e4dc971ef51817d5ab3c7a3a8">More...</a><br/></td></tr>
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<tr class="memitem:gaaf2c3d5ccd811cd525971db6edc37183"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gaaf2c3d5ccd811cd525971db6edc37183">XNANDPS_ECC_MEMCFG_ECC_MODE_SHIFT</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:gaaf2c3d5ccd811cd525971db6edc37183"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc cfg ecc_mode shift.  <a href="group__nandps.html#gaaf2c3d5ccd811cd525971db6edc37183">More...</a><br/></td></tr>
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<tr class="memitem:gac7b61519733a4be05a029c4767dcf624"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gac7b61519733a4be05a029c4767dcf624">XNANDPS_ECC_MEMCFG_ECC_READ_END_SHIFT</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:gac7b61519733a4be05a029c4767dcf624"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc cfg ecc_read_end shift.  <a href="group__nandps.html#gac7b61519733a4be05a029c4767dcf624">More...</a><br/></td></tr>
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<tr class="memitem:ga626e312c59becf9175883314824ee42d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga626e312c59becf9175883314824ee42d">XNANDPS_ECC_MEMCFG_ECC_JUMP_SHIFT</a>&#160;&#160;&#160;5</td></tr>
<tr class="memdesc:ga626e312c59becf9175883314824ee42d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc cfg ecc_jump shift.  <a href="group__nandps.html#ga626e312c59becf9175883314824ee42d">More...</a><br/></td></tr>
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<tr class="memitem:ga342ff07bb404de4c4e6187497ff04e92"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga342ff07bb404de4c4e6187497ff04e92">XNANDPS_ECC_MEMCFG_IGNORE_ADD8_SHIFT</a>&#160;&#160;&#160;7</td></tr>
<tr class="memdesc:ga342ff07bb404de4c4e6187497ff04e92"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc cfg ecc_ignore_add_eight shift.  <a href="group__nandps.html#ga342ff07bb404de4c4e6187497ff04e92">More...</a><br/></td></tr>
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<tr class="memitem:ga4fe5b2818be2687b9ae9678f26209a79"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga4fe5b2818be2687b9ae9678f26209a79">XNANDPS_ECC_MEMCFG_ECC_INT_PASS_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:ga4fe5b2818be2687b9ae9678f26209a79"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc cfg ecc_int_pass shift.  <a href="group__nandps.html#ga4fe5b2818be2687b9ae9678f26209a79">More...</a><br/></td></tr>
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<tr class="memitem:ga8c4855e539e3e9d9eb6312f5a85cddfa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga8c4855e539e3e9d9eb6312f5a85cddfa">XNANDPS_ECC_MEMCFG_ECC_INT_ABORT_SHIFT</a>&#160;&#160;&#160;9</td></tr>
<tr class="memdesc:ga8c4855e539e3e9d9eb6312f5a85cddfa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc cfg ecc_int_abort shift.  <a href="group__nandps.html#ga8c4855e539e3e9d9eb6312f5a85cddfa">More...</a><br/></td></tr>
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<tr class="memitem:gabd615b4b5a0bd6122af9b92b4a87030c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gabd615b4b5a0bd6122af9b92b4a87030c">XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SHIFT</a>&#160;&#160;&#160;10</td></tr>
<tr class="memdesc:gabd615b4b5a0bd6122af9b92b4a87030c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc cfg ecc_extra_block shift.  <a href="group__nandps.html#gabd615b4b5a0bd6122af9b92b4a87030c">More...</a><br/></td></tr>
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<tr class="memitem:gaa986c04140bbeb60f11a573e90b94dbd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#gaa986c04140bbeb60f11a573e90b94dbd">XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SIZE_SHIFT</a>&#160;&#160;&#160;11</td></tr>
<tr class="memdesc:gaa986c04140bbeb60f11a573e90b94dbd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc cfg ecc_extra_block_size shift.  <a href="group__nandps.html#gaa986c04140bbeb60f11a573e90b94dbd">More...</a><br/></td></tr>
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<tr class="memitem:ga5d6d2d29177affe9bdc2a66308b02341"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga5d6d2d29177affe9bdc2a66308b02341">XNANDPS_ECC_MEMCFG_PAGE_SIZE_512</a>&#160;&#160;&#160;0x1</td></tr>
<tr class="memdesc:ga5d6d2d29177affe9bdc2a66308b02341"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECC cfg page size value for 512 byte page.  <a href="group__nandps.html#ga5d6d2d29177affe9bdc2a66308b02341">More...</a><br/></td></tr>
<tr class="separator:ga5d6d2d29177affe9bdc2a66308b02341"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga36f170edfdc0206eb7a33071f9f4cf9d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga36f170edfdc0206eb7a33071f9f4cf9d">XNANDPS_ECC_MEMCFG_PAGE_SIZE_1024</a>&#160;&#160;&#160;0x2</td></tr>
<tr class="memdesc:ga36f170edfdc0206eb7a33071f9f4cf9d"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECC cfg page size value for 1024 byte page.  <a href="group__nandps.html#ga36f170edfdc0206eb7a33071f9f4cf9d">More...</a><br/></td></tr>
<tr class="separator:ga36f170edfdc0206eb7a33071f9f4cf9d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7d9edc9df98df1d1616cbb62bb8741fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandps.html#ga7d9edc9df98df1d1616cbb62bb8741fe">XNANDPS_ECC_MEMCFG_PAGE_SIZE_2048</a>&#160;&#160;&#160;0x3</td></tr>
<tr class="memdesc:ga7d9edc9df98df1d1616cbb62bb8741fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECC cfg page size value for 2048 byte page.  <a href="group__nandps.html#ga7d9edc9df98df1d1616cbb62bb8741fe">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">ECC mem command1 register bit definitions and masks and shifts</div></td></tr>
<tr class="memitem:ad0f1d158ff4c217d7a28a9c577df4cdb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#ad0f1d158ff4c217d7a28a9c577df4cdb">XNANDPS_ECC_MEMCOMMAND1_WR_CMD_MASK</a>&#160;&#160;&#160;0x000000FF</td></tr>
<tr class="memdesc:ad0f1d158ff4c217d7a28a9c577df4cdb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc command 1 nand_wr_cmd mask.  <a href="#ad0f1d158ff4c217d7a28a9c577df4cdb">More...</a><br/></td></tr>
<tr class="separator:ad0f1d158ff4c217d7a28a9c577df4cdb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a428d8145336e48df7157267d674734ad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#a428d8145336e48df7157267d674734ad">XNANDPS_ECC_MEMCOMMAND1_RD_CMD_MASK</a>&#160;&#160;&#160;0x0000FF00</td></tr>
<tr class="memdesc:a428d8145336e48df7157267d674734ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc command 1 nand_rd_cmd mask.  <a href="#a428d8145336e48df7157267d674734ad">More...</a><br/></td></tr>
<tr class="separator:a428d8145336e48df7157267d674734ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a61b7f37efec7bf8fe2281a9f14380764"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#a61b7f37efec7bf8fe2281a9f14380764">XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_MASK</a>&#160;&#160;&#160;0x00FF0000</td></tr>
<tr class="memdesc:a61b7f37efec7bf8fe2281a9f14380764"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc command 1 nand_rd_cmd_end mask.  <a href="#a61b7f37efec7bf8fe2281a9f14380764">More...</a><br/></td></tr>
<tr class="separator:a61b7f37efec7bf8fe2281a9f14380764"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a03fd8c5deeae17b62baa533120b96527"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#a03fd8c5deeae17b62baa533120b96527">XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_VALID_MASK</a>&#160;&#160;&#160;0x01000000</td></tr>
<tr class="memdesc:a03fd8c5deeae17b62baa533120b96527"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc command 1 nand_rd_cmd_end_valid mask.  <a href="#a03fd8c5deeae17b62baa533120b96527">More...</a><br/></td></tr>
<tr class="separator:a03fd8c5deeae17b62baa533120b96527"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a91a88936d7883eb8a46d2ae5e0b38543"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#a91a88936d7883eb8a46d2ae5e0b38543">XNANDPS_ECC_MEMCOMMAND1_WR_CMD_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:a91a88936d7883eb8a46d2ae5e0b38543"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc command 1 nand_wr_cmd shift.  <a href="#a91a88936d7883eb8a46d2ae5e0b38543">More...</a><br/></td></tr>
<tr class="separator:a91a88936d7883eb8a46d2ae5e0b38543"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6c3123982a9b5da195d9530d541cd06f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#a6c3123982a9b5da195d9530d541cd06f">XNANDPS_ECC_MEMCOMMAND1_RD_CMD_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:a6c3123982a9b5da195d9530d541cd06f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc command 1 nand_rd_cmd shift.  <a href="#a6c3123982a9b5da195d9530d541cd06f">More...</a><br/></td></tr>
<tr class="separator:a6c3123982a9b5da195d9530d541cd06f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3d48d8af5b0f09ee1105069caf32c920"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#a3d48d8af5b0f09ee1105069caf32c920">XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a3d48d8af5b0f09ee1105069caf32c920"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc command 1 nand_rd_cmd_end shift.  <a href="#a3d48d8af5b0f09ee1105069caf32c920">More...</a><br/></td></tr>
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<tr class="memitem:a8cb896a4cbb6e8b643bcab62b36daff8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#a8cb896a4cbb6e8b643bcab62b36daff8">XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_VALID_SHIFT</a>&#160;&#160;&#160;24</td></tr>
<tr class="memdesc:a8cb896a4cbb6e8b643bcab62b36daff8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc command 1 nand_rd_cmd_end_valid shift.  <a href="#a8cb896a4cbb6e8b643bcab62b36daff8">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">ECC mem command2 register bit definitions and masks</div></td></tr>
<tr class="memitem:a0bcbf0cc78a3e55dae33392332bc944b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#a0bcbf0cc78a3e55dae33392332bc944b">XNANDPS_ECC_MEMCOMMAND2_WR_COL_CHANGE_MASK</a>&#160;&#160;&#160;0x000000FF</td></tr>
<tr class="memdesc:a0bcbf0cc78a3e55dae33392332bc944b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc command2 nand_wr_col_change mask.  <a href="#a0bcbf0cc78a3e55dae33392332bc944b">More...</a><br/></td></tr>
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<tr class="memitem:aa5a0051020589e08af6ff6657b400d25"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#aa5a0051020589e08af6ff6657b400d25">XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_MASK</a>&#160;&#160;&#160;0x0000FF00</td></tr>
<tr class="memdesc:aa5a0051020589e08af6ff6657b400d25"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc command2 nand_rd_col_change mask.  <a href="#aa5a0051020589e08af6ff6657b400d25">More...</a><br/></td></tr>
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<tr class="memitem:a247ad27dc8366a9c9d4b758d9d216ce3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#a247ad27dc8366a9c9d4b758d9d216ce3">XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_MASK</a>&#160;&#160;&#160;0x00FF0000</td></tr>
<tr class="memdesc:a247ad27dc8366a9c9d4b758d9d216ce3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc command2 nand_rd_col_change_end mask.  <a href="#a247ad27dc8366a9c9d4b758d9d216ce3">More...</a><br/></td></tr>
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<tr class="memitem:a9058790608f7c5486ea59bea4985aca0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#a9058790608f7c5486ea59bea4985aca0">XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_VALID_MASK</a>&#160;&#160;&#160;0x00FF0000</td></tr>
<tr class="memdesc:a9058790608f7c5486ea59bea4985aca0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc command2 nand_rd_col_change_end_valid mask.  <a href="#a9058790608f7c5486ea59bea4985aca0">More...</a><br/></td></tr>
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<tr class="memitem:a0370d409026629c9c67c6a09356168b7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#a0370d409026629c9c67c6a09356168b7">XNANDPS_ECC_MEMCOMMAND2_WR_COL_CHANGE_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:a0370d409026629c9c67c6a09356168b7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc command2 nand_wr_col_change shift.  <a href="#a0370d409026629c9c67c6a09356168b7">More...</a><br/></td></tr>
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<tr class="memitem:a2268559b8b7eda4b64e06be46c1ae163"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#a2268559b8b7eda4b64e06be46c1ae163">XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:a2268559b8b7eda4b64e06be46c1ae163"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc command2 nand_rd_col_change shift.  <a href="#a2268559b8b7eda4b64e06be46c1ae163">More...</a><br/></td></tr>
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<tr class="memitem:a1ac7be4acb6465855e90c59a917ea460"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#a1ac7be4acb6465855e90c59a917ea460">XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a1ac7be4acb6465855e90c59a917ea460"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc command2 nand_rd_col_change_end shift.  <a href="#a1ac7be4acb6465855e90c59a917ea460">More...</a><br/></td></tr>
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<tr class="memitem:a9affb1a5cbc15106387b90f11585d316"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#a9affb1a5cbc15106387b90f11585d316">XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_VALID_SHIFT</a>&#160;&#160;&#160;24</td></tr>
<tr class="memdesc:a9affb1a5cbc15106387b90f11585d316"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc command2 nand_rd_col_change_end_valid shift.  <a href="#a9affb1a5cbc15106387b90f11585d316">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">ECC value register bit definitions and masks</div></td></tr>
<tr class="memitem:abd321ba9d00a905039b840f384953fe0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#abd321ba9d00a905039b840f384953fe0">XNANDPS_ECC_VALUE_MASK</a>&#160;&#160;&#160;0x00FFFFFF</td></tr>
<tr class="memdesc:abd321ba9d00a905039b840f384953fe0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc value ecc_value mask.  <a href="#abd321ba9d00a905039b840f384953fe0">More...</a><br/></td></tr>
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<tr class="memitem:a99dba6f69078ff5cb8ab74caef49e58e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#a99dba6f69078ff5cb8ab74caef49e58e">XNANDPS_ECC_VALUE_CORRECT_MASK</a>&#160;&#160;&#160;0x08000000</td></tr>
<tr class="memdesc:a99dba6f69078ff5cb8ab74caef49e58e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc value ecc_correct mask.  <a href="#a99dba6f69078ff5cb8ab74caef49e58e">More...</a><br/></td></tr>
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<tr class="memitem:a8b01a9e54854f1a4500fdaa17d9ac3f7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#a8b01a9e54854f1a4500fdaa17d9ac3f7">XNANDPS_ECC_VALUE_FAIL_MASK</a>&#160;&#160;&#160;0x10000000</td></tr>
<tr class="memdesc:a8b01a9e54854f1a4500fdaa17d9ac3f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc value ecc_fail mask.  <a href="#a8b01a9e54854f1a4500fdaa17d9ac3f7">More...</a><br/></td></tr>
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<tr class="memitem:a979da85b08795805ac5f983d7ff9c966"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#a979da85b08795805ac5f983d7ff9c966">XNANDPS_ECC_VALUE_READ_MASK</a>&#160;&#160;&#160;0x20000000</td></tr>
<tr class="memdesc:a979da85b08795805ac5f983d7ff9c966"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc value ecc_read mask.  <a href="#a979da85b08795805ac5f983d7ff9c966">More...</a><br/></td></tr>
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<tr class="memitem:a210a51bf0a539aa77d6bd462277dc6a5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#a210a51bf0a539aa77d6bd462277dc6a5">XNANDPS_ECC_VALUE_VALID_MASK</a>&#160;&#160;&#160;0x40000000</td></tr>
<tr class="memdesc:a210a51bf0a539aa77d6bd462277dc6a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ecc value ecc_valid mask.  <a href="#a210a51bf0a539aa77d6bd462277dc6a5">More...</a><br/></td></tr>
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<tr class="memitem:abf89911aba671967dca41b8cbb4388c2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#abf89911aba671967dca41b8cbb4388c2">XNANDPS_ECC_VALUE_INT_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Peripheral ID register bit definitions and masks</div></td></tr>
<tr class="memitem:a603f4aba36490d2ef26cbbf21b6cc661"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#a603f4aba36490d2ef26cbbf21b6cc661">XNANDPS_PERIPH_ID_PART_NUM_MASK</a>&#160;&#160;&#160;0x00000FFF</td></tr>
<tr class="memdesc:a603f4aba36490d2ef26cbbf21b6cc661"><td class="mdescLeft">&#160;</td><td class="mdescRight">Peripheral ID part_num mask.  <a href="#a603f4aba36490d2ef26cbbf21b6cc661">More...</a><br/></td></tr>
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<tr class="memitem:a77e665a6416e29cf5142ef012c95df79"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#a77e665a6416e29cf5142ef012c95df79">XNANDPS_PERIPH_ID_DESIGNER_ID_MASK</a>&#160;&#160;&#160;0x000FF000</td></tr>
<tr class="memdesc:a77e665a6416e29cf5142ef012c95df79"><td class="mdescLeft">&#160;</td><td class="mdescRight">Peripheral ID designed id mask.  <a href="#a77e665a6416e29cf5142ef012c95df79">More...</a><br/></td></tr>
<tr class="separator:a77e665a6416e29cf5142ef012c95df79"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae1e0ae792930c07ff33930814b9699f8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#ae1e0ae792930c07ff33930814b9699f8">XNANDPS_PERIPH_ID_REVISION_MASK</a>&#160;&#160;&#160;0x00F00000</td></tr>
<tr class="memdesc:ae1e0ae792930c07ff33930814b9699f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Peripheral ID revision mask.  <a href="#ae1e0ae792930c07ff33930814b9699f8">More...</a><br/></td></tr>
<tr class="separator:ae1e0ae792930c07ff33930814b9699f8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abc9a59890b46122178dbd56ce3dd0f63"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#abc9a59890b46122178dbd56ce3dd0f63">XNANDPS_PERIPH_ID_INTG_CFG_MASK</a>&#160;&#160;&#160;0x01000000</td></tr>
<tr class="memdesc:abc9a59890b46122178dbd56ce3dd0f63"><td class="mdescLeft">&#160;</td><td class="mdescRight">Peripheral ID integration_cfg mask.  <a href="#abc9a59890b46122178dbd56ce3dd0f63">More...</a><br/></td></tr>
<tr class="separator:abc9a59890b46122178dbd56ce3dd0f63"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a95afea81f67fc8928dba1a8b108d58cf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xnandps__hw_8h.html#a95afea81f67fc8928dba1a8b108d58cf">XNANDPS_PCELL_ID_MASK</a>&#160;&#160;&#160;0x000000FF</td></tr>
<tr class="memdesc:a95afea81f67fc8928dba1a8b108d58cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Primecell identification register mask.  <a href="#a95afea81f67fc8928dba1a8b108d58cf">More...</a><br/></td></tr>
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</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="a61b7f37efec7bf8fe2281a9f14380764"></a>
<div class="memitem">
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          <td class="memname">#define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_MASK&#160;&#160;&#160;0x00FF0000</td>
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      </table>
</div><div class="memdoc">

<p>Ecc command 1 nand_rd_cmd_end mask. </p>

</div>
</div>
<a class="anchor" id="a3d48d8af5b0f09ee1105069caf32c920"></a>
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          <td class="memname">#define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_SHIFT&#160;&#160;&#160;16</td>
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</div><div class="memdoc">

<p>Ecc command 1 nand_rd_cmd_end shift. </p>

</div>
</div>
<a class="anchor" id="a03fd8c5deeae17b62baa533120b96527"></a>
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          <td class="memname">#define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_VALID_MASK&#160;&#160;&#160;0x01000000</td>
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      </table>
</div><div class="memdoc">

<p>Ecc command 1 nand_rd_cmd_end_valid mask. </p>

<p>Referenced by <a class="el" href="group__nandps.html#ga605bd783f065806f1d1f602f88128f9b">XNandPs_ReadCache()</a>.</p>

</div>
</div>
<a class="anchor" id="a8cb896a4cbb6e8b643bcab62b36daff8"></a>
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          <td class="memname">#define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_VALID_SHIFT&#160;&#160;&#160;24</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Ecc command 1 nand_rd_cmd_end_valid shift. </p>

</div>
</div>
<a class="anchor" id="a428d8145336e48df7157267d674734ad"></a>
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          <td class="memname">#define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_MASK&#160;&#160;&#160;0x0000FF00</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Ecc command 1 nand_rd_cmd mask. </p>

</div>
</div>
<a class="anchor" id="a6c3123982a9b5da195d9530d541cd06f"></a>
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          <td class="memname">#define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Ecc command 1 nand_rd_cmd shift. </p>

</div>
</div>
<a class="anchor" id="ad0f1d158ff4c217d7a28a9c577df4cdb"></a>
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          <td class="memname">#define XNANDPS_ECC_MEMCOMMAND1_WR_CMD_MASK&#160;&#160;&#160;0x000000FF</td>
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      </table>
</div><div class="memdoc">

<p>Ecc command 1 nand_wr_cmd mask. </p>

</div>
</div>
<a class="anchor" id="a91a88936d7883eb8a46d2ae5e0b38543"></a>
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          <td class="memname">#define XNANDPS_ECC_MEMCOMMAND1_WR_CMD_SHIFT&#160;&#160;&#160;0</td>
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      </table>
</div><div class="memdoc">

<p>Ecc command 1 nand_wr_cmd shift. </p>

</div>
</div>
<a class="anchor" id="a247ad27dc8366a9c9d4b758d9d216ce3"></a>
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          <td class="memname">#define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_MASK&#160;&#160;&#160;0x00FF0000</td>
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      </table>
</div><div class="memdoc">

<p>Ecc command2 nand_rd_col_change_end mask. </p>

</div>
</div>
<a class="anchor" id="a1ac7be4acb6465855e90c59a917ea460"></a>
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          <td class="memname">#define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_SHIFT&#160;&#160;&#160;16</td>
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      </table>
</div><div class="memdoc">

<p>Ecc command2 nand_rd_col_change_end shift. </p>

</div>
</div>
<a class="anchor" id="a9058790608f7c5486ea59bea4985aca0"></a>
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          <td class="memname">#define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_VALID_MASK&#160;&#160;&#160;0x00FF0000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Ecc command2 nand_rd_col_change_end_valid mask. </p>

</div>
</div>
<a class="anchor" id="a9affb1a5cbc15106387b90f11585d316"></a>
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          <td class="memname">#define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_VALID_SHIFT&#160;&#160;&#160;24</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Ecc command2 nand_rd_col_change_end_valid shift. </p>

</div>
</div>
<a class="anchor" id="aa5a0051020589e08af6ff6657b400d25"></a>
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          <td class="memname">#define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_MASK&#160;&#160;&#160;0x0000FF00</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Ecc command2 nand_rd_col_change mask. </p>

</div>
</div>
<a class="anchor" id="a2268559b8b7eda4b64e06be46c1ae163"></a>
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          <td class="memname">#define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_SHIFT&#160;&#160;&#160;8</td>
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<p>Ecc command2 nand_rd_col_change shift. </p>

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<a class="anchor" id="a0bcbf0cc78a3e55dae33392332bc944b"></a>
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          <td class="memname">#define XNANDPS_ECC_MEMCOMMAND2_WR_COL_CHANGE_MASK&#160;&#160;&#160;0x000000FF</td>
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<p>Ecc command2 nand_wr_col_change mask. </p>

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<a class="anchor" id="a0370d409026629c9c67c6a09356168b7"></a>
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<div class="memproto">
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          <td class="memname">#define XNANDPS_ECC_MEMCOMMAND2_WR_COL_CHANGE_SHIFT&#160;&#160;&#160;0</td>
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<p>Ecc command2 nand_wr_col_change shift. </p>

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<a class="anchor" id="a99dba6f69078ff5cb8ab74caef49e58e"></a>
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          <td class="memname">#define XNANDPS_ECC_VALUE_CORRECT_MASK&#160;&#160;&#160;0x08000000</td>
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</div><div class="memdoc">

<p>Ecc value ecc_correct mask. </p>

</div>
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<a class="anchor" id="a8b01a9e54854f1a4500fdaa17d9ac3f7"></a>
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<div class="memproto">
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          <td class="memname">#define XNANDPS_ECC_VALUE_FAIL_MASK&#160;&#160;&#160;0x10000000</td>
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<p>Ecc value ecc_fail mask. </p>

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<a class="anchor" id="abf89911aba671967dca41b8cbb4388c2"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XNANDPS_ECC_VALUE_INT_MASK&#160;&#160;&#160;0x80000000</td>
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<p>Ecc value ecc_int mask. </p>

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</div>
<a class="anchor" id="abd321ba9d00a905039b840f384953fe0"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XNANDPS_ECC_VALUE_MASK&#160;&#160;&#160;0x00FFFFFF</td>
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<p>Ecc value ecc_value mask. </p>

</div>
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<a class="anchor" id="a979da85b08795805ac5f983d7ff9c966"></a>
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<div class="memproto">
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          <td class="memname">#define XNANDPS_ECC_VALUE_READ_MASK&#160;&#160;&#160;0x20000000</td>
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<p>Ecc value ecc_read mask. </p>

</div>
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<a class="anchor" id="a210a51bf0a539aa77d6bd462277dc6a5"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XNANDPS_ECC_VALUE_VALID_MASK&#160;&#160;&#160;0x40000000</td>
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      </table>
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<p>Ecc value ecc_valid mask. </p>

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<a class="anchor" id="a95afea81f67fc8928dba1a8b108d58cf"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XNANDPS_PCELL_ID_MASK&#160;&#160;&#160;0x000000FF</td>
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<p>Primecell identification register mask. </p>

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<a class="anchor" id="a77e665a6416e29cf5142ef012c95df79"></a>
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<div class="memproto">
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          <td class="memname">#define XNANDPS_PERIPH_ID_DESIGNER_ID_MASK&#160;&#160;&#160;0x000FF000</td>
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<p>Peripheral ID designed id mask. </p>

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<a class="anchor" id="abc9a59890b46122178dbd56ce3dd0f63"></a>
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          <td class="memname">#define XNANDPS_PERIPH_ID_INTG_CFG_MASK&#160;&#160;&#160;0x01000000</td>
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<p>Peripheral ID integration_cfg mask. </p>

</div>
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<a class="anchor" id="a603f4aba36490d2ef26cbbf21b6cc661"></a>
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          <td class="memname">#define XNANDPS_PERIPH_ID_PART_NUM_MASK&#160;&#160;&#160;0x00000FFF</td>
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      </table>
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<p>Peripheral ID part_num mask. </p>

</div>
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<a class="anchor" id="ae1e0ae792930c07ff33930814b9699f8"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XNANDPS_PERIPH_ID_REVISION_MASK&#160;&#160;&#160;0x00F00000</td>
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      </table>
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<p>Peripheral ID revision mask. </p>

</div>
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<a class="anchor" id="ab1c9ec799c4b10aba366c1333b36d98b"></a>
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          <td class="memname">#define XNandPs_ReadReg&#160;&#160;&#160;Xil_In32</td>
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<p>XNandPs Register register. </p>

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</div>
<a class="anchor" id="ac87bcc9e0fec61b2b02b9a434962e576"></a>
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          <td class="memname">#define XNandPs_WriteReg&#160;&#160;&#160;Xil_Out32</td>
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<p>XNandPs register write. </p>

<p>Referenced by <a class="el" href="group__nandps.html#gaddb9f847fae34f6d137f591375a7c962">XNandPs_CfgInitialize()</a>, <a class="el" href="group__nandps.html#ga22b4e2bc1af7e4bfecd4428c25a77bb8">XNandPs_EraseBlock()</a>, <a class="el" href="group__nandps.html#ga8e72425d265074f1c2f8c66edfd22857">XNandPs_Read()</a>, <a class="el" href="group__nandps.html#ga605bd783f065806f1d1f602f88128f9b">XNandPs_ReadCache()</a>, <a class="el" href="group__nandps.html#gaf9857df5e1359875e429f66e46ca5a86">XNandPs_ReadSpareBytes()</a>, <a class="el" href="group__nandps.html#gae2862ccd7e9180b843d9e73e2a8c7e7b">XNandPs_SendCommand()</a>, and <a class="el" href="group__nandps.html#gaa987d756af43c965a6439f077a4ce158">XNandPs_WriteSpareBytes()</a>.</p>

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